Pixel Memory Inverter Circuit for Hardware Video Scrolling
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Solution Overview
Problem
Existing liquid crystal display devices with memory units in each pixel cannot read data values stored in the memory units, limiting the ability to perform video movement or scrolling without software assistance.
Innovation Solution
Incorporating a first and second inverter circuit with transistors and a logic circuit that controls scanning lines to enable reading and writing of data values, allowing direct data transfer between memory units in the display pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If a memory unit is arranged in each display pixel to store video data, then an image can be displayed even when there is no input signal, but the data value stored in the memory unit cannot be read
Solution Approach 1:
A read control signal is introduced as an intermediary to control the reading operation. When the read control signal is activated, it enables the transistor connected to the video line, allowing the stored data to be read out. This mediator resolves the contradiction by providing a controlled mechanism to access stored data when needed while maintaining the memory function when the signal is inactive.
2Productivity
If transistors are added to enable reading and writing of data values in memory units, then direct data transfer between pixels becomes possible, but the device complexity increases
Solution Approach 1:
The video line and existing transistors are designed to serve multiple functions. The same video line structure is used for both writing data to memory units and reading data from them. The transistor connected to the video line can operate in different modes (writing mode when read control signal is low, reading mode when read control signal is high), eliminating the need for completely separate read/write circuitry and reducing overall device complexity.
Data Source
AI summary
A display device includes a memory unit formed in each pixel to store video data and including a first inverter circuit whose input terminal is connected to a first node and whose output terminal is connected to a second node and a second inverter circuit whose input terminal is connected to the second node and whose output terminal is connected to the first node, a first transistor connected between the output terminal of the second inverter circuit and the video line, and a second transistor connected between the first node and the video line, in which at the time of reading the video data, the first transistor is turned ON, and the second transistor is turned OFF, to output the video data stored in the memory unit to the video line.


