Image Sensor Pixel Noise Reduction via Parasitic Capacitance
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Solution Overview
Problem
Miniaturization of image sensors leads to smaller photodiodes, resulting in smaller charge generation and increased susceptibility to noise, with current techniques to reduce pixel readout noise requiring larger die sizes or degrading photodiode sensitivity.
Innovation Solution
The implementation of an arrangement of circuitry that increases parasitic capacitance between bit line traces and other traces, with segments extending in parallel to reduce noise, while maintaining a minimal separation to avoid increasing the image sensor size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large sample hold capacitance is provided in the CDS circuit to reduce pixel readout noise, then signal-to-noise characteristics are improved, but the die size increases
Solution Approach 1:
The patent extracts the noise reduction function from the traditional large capacitance approach and implements it through a different mechanism - using a small capacitance in combination with a specific switching sequence that achieves correlated double sampling without requiring large energy storage elements, thereby reducing die size while maintaining signal-to-noise characteristics
Solution Approach 2:
The patent changes the operational parameters by using a multi-stage switching sequence with specific timing relationships between switches S1-S4 and capacitors C1-C2, transforming the noise reduction mechanism from passive large-capacitance filtering to active sequential sampling with small capacitances
2Reliability
If a large gate size is provided for source follower transistor T3 to reduce pixel readout noise, then signal-to-noise characteristics are improved, but photodiode size decreases which degrades sensitivity and full-well capacity
Solution Approach 1:
The patent extracts the noise reduction function from the source follower transistor gate size and relocates it to the correlated double sampling circuitry, allowing the source follower to maintain a small gate size that preserves photodiode area while achieving noise reduction through the sequential sampling mechanism
Solution Approach 2:
The patent introduces intermediate sampling capacitors C1 and C2 that act as mediators between the photodiode and the readout circuitry, enabling noise reduction through correlated double sampling without requiring the source follower transistor to have a large gate size, thus preserving photodiode sensitivity and full-well capacity
3Productivity
If miniaturization is implemented in image sensors to achieve higher resolution and lower power consumption, then integration is improved, but photodiodes become smaller generating smaller charge which increases susceptibility to noise
Solution Approach 1:
The patent implements a feedback mechanism through the correlated double sampling process where the first sample (taken before charge transfer) is subtracted from the second sample (taken after charge transfer), effectively canceling out common-mode noise and allowing miniaturized photodiodes to maintain signal integrity despite smaller charge generation
Solution Approach 2:
The patent introduces floating diffusion nodes and sampling capacitors as intermediary elements that buffer and condition the small charge signals from miniaturized photodiodes, enabling effective noise reduction through sequential sampling without requiring larger photodiode areas, thus maintaining both integration benefits and signal reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces pixel readout signal noise without compromising photodiode sensitivity or increasing the image sensor size, thereby improving signal-to-noise characteristics.
Implementation Method 1
arrangement of circuitry to increase parasitic capacitance between bit line trace and one or more other traces
Data Source
AI summary
Circuitry to reduce signal noise characteristics in an image sensor. In an embodiment, a bit trace line segment is located between neighboring respective segments of a source follower power trace and an additional trace which is to remain at a first voltage level during a pixel cell readout time period. In another embodiment, for each such trace segment, a smallest separation between the trace segment and the respective neighboring other one of such trace segments is substantially equal to or less than some maximum length to provide for parasitic capacitance between the bit line trace and one or more other traces.