Pixel Electrode Overlap Layout for Lower Data Line Crosstalk
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Solution Overview
Problem
Display devices face challenges in reducing parasitic capacitance between pixel electrodes and data lines, leading to deviations in display quality, particularly in light emitting diode (LED) displays which affect image clarity and luminance consistency.
Innovation Solution
The design includes specific arrangements of pixel circuit portions, transistors, and data lines, where pixel electrodes overlap data lines in a controlled manner to minimize parasitic capacitance, with varying electrode areas and orientations to optimize overlap and reduce capacitance fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If pixel electrodes are arranged to overlap data lines to simplify layout, then device complexity is reduced, but parasitic capacitance increases causing display quality degradation
Solution Approach 1:
The patent applies local quality by making different pixel electrodes have different overlapping characteristics with data lines. Specifically, a first pixel electrode overlaps a data line while a second pixel electrode does not overlap the data line, or overlaps it to a different extent. This localized differentiation reduces parasitic capacitance in critical areas while maintaining layout simplicity elsewhere, thereby improving display quality without significantly increasing device complexity.
2Manufacturing precision
If all pixel electrodes overlap data lines uniformly, then manufacturing precision is simplified, but display quality deteriorates due to varying parasitic capacitance across pixels
Solution Approach 1:
The patent implements local quality by specifying that different pixel electrodes have different overlapping relationships with data lines. The first pixel electrode overlaps the data line while the second pixel electrode does not overlap or overlaps to a lesser extent. This creates localized variations in parasitic capacitance compensation that improve overall display quality consistency while maintaining relatively simple manufacturing processes.
3Reliability
If parasitic capacitance is reduced by minimizing electrode overlap, then display quality improves, but manufacturing complexity increases due to varied electrode configurations
Solution Approach 1:
The patent resolves this contradiction by applying local quality principles to the electrode configuration. Instead of making all electrodes complex, only specific pixel electrodes (the first pixel electrode) have overlapping arrangements with data lines, while others (the second pixel electrode) do not. This selective approach reduces parasitic capacitance and improves display quality while keeping the overall manufacturing process relatively simple.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance and crosstalk, enhancing display quality by maintaining consistent voltage and current across pixels, thereby improving image clarity and luminance uniformity.
Implementation Method 1
a first pixel electrode electrically connected to the first pixel circuit portion; a second pixel electrode electrically connected to the second pixel circuit portion... the second pixel electrode overlaps the first data line and the second data line in a plan view
Data Source
AI summary
The present disclosure relates to a display device, and the display device according to an exemplary embodiment of the present inventive concept includes: a first pixel circuit portion including at least one transistor; a second pixel circuit portion including at least one transistor; a first pixel electrode electrically connected to the first pixel circuit portion; a second pixel electrode electrically connected to the second pixel circuit portion; a first data line electrically connected to the first pixel circuit portion; and a second data line electrically connected to the second pixel circuit portion, wherein the first data line and the second data line are arranged adjacent to each other along a first direction, and the second pixel electrode overlaps the first data line and the second data line in a plan view.