Contiguous Pixel Packing in Cache Lines
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Solution Overview
Problem
Existing cache systems face inefficiencies when storing 24-bit pixels due to non-whole number multiples of bits per pixel, leading to partial data storage across cache lines, resulting in wasted space and increased memory accesses.
Innovation Solution
Storing multiple discrete data elements contiguously in cache lines and addressable storage units, ensuring no data element is split across lines or units, thereby optimizing memory usage and reducing unused space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 24-bit pixels are stored contiguously in cache lines without alignment to cache line boundaries, then memory space utilization improves, but data elements may be split across multiple cache lines requiring multiple memory accesses
Solution Approach 1:
The invention segments the pixel storage problem by introducing a new data structure (pixel pack) that contains a specific number of pixels (e.g., 7 pixels × 24 bits = 168 bits) that fits within a cache line boundary. This segmentation allows complete pixel data to be stored and retrieved in single cache line accesses, eliminating the data splitting problem while maximizing cache line utilization.
Solution Approach 2:
The invention changes the storage parameters by organizing pixels into packs with specific counts that are multiples of the cache line size divided by the pixel size. For example, storing 7 pixels per 16-byte cache line (7×24=168 bits) or 10 pixels per 20-byte cache line (10×24=240 bits) ensures that pixel data aligns with cache line boundaries, preventing partial pixel storage across multiple lines.
2Reliability
If 24-bit pixels are stored with 8-bit padding between each pixel, then data element integrity is maintained, but memory space utilization decreases to 75% efficiency
Solution Approach 1:
The invention extracts the unnecessary padding bytes from the storage structure. Instead of allocating 8 bits of padding after each 24-bit pixel, the patent removes these redundant spaces and reallocates the cache line capacity to store more complete pixel data, achieving higher density without compromising data integrity.
Solution Approach 2:
The invention merges multiple pixels into packs that fill cache lines more efficiently. By combining 7 pixels (168 bits) or 10 pixels (240 bits) into single cache line structures, the patent eliminates the need for individual pixel padding and achieves better space utilization through consolidated storage units.
3Productivity
If cache lines are fully utilized to store maximum number of pixels, then productivity increases, but the complexity of managing partial cache lines increases
Solution Approach 1:
The invention performs preliminary organization of pixels into fixed-size packs before storing them in cache lines. By pre-defining pixel pack structures (e.g., 7-pixel packs, 10-pixel packs) that align with cache line boundaries, the system eliminates the need for complex runtime calculations to determine how many pixels fit in each cache line, simplifying cache management.
Solution Approach 2:
The invention introduces dynamic pixel pack structures that can be configured based on cache line size and pixel format. The system can adaptively determine the number of pixels per pack (e.g., adjusting between 7 or 10 pixels per cache line) to optimize for different hardware configurations, providing flexibility without increasing management complexity.
Data Source
AI summary
Data for data elements (e.g., pixels) can be stored in an addressable storage unit that can store a number of bits that is not a whole number multiple of the number of bits of data per data element. Similarly, a number of the data elements can be transferred per unit of time over a bus, where the width of the bus is not a whole number multiple of the number of bits of data per data element. Data for none of the data elements is stored in more than one of the storage units or transferred in more than one unit of time. Also, data for multiple data elements is packaged contiguously in the storage unit or across the width of the bus.