Pixel Position Pipeline Circuit for High-Speed Holographic Displays

The patent divides the pixel position value generation into multiple segments by using several pipeline modules (e.g., 4 pipeline modules) that each handle a portion of the output stream. Each pipeline module receives the same input from the single unity addition module but processes and outputs different segments of the pixel position values, thereby increasing the overall output speed without requiring multiple addition modules.

The patent transitions from a single-dimensional sequential output to a multi-dimensional parallel output structure. By introducing multiple pipeline modules that operate in parallel, the system expands the output dimensionality, allowing multiple pixel position values to be generated simultaneously from a single input stream, thus increasing productivity while maintaining component simplicity.

The patent merges multiple pipeline modules into a unified structure that shares a common input source (the single unity addition module). This merging approach allows the system to achieve high productivity through parallel processing while avoiding the complexity of having completely independent generation modules for each pipeline, as they all receive and process the same input stream.

Each pipeline module is designed to be universal and multi-functional, capable of processing the same input type (pixel position values from the unity addition module) and producing different segments of the output stream. This universality reduces the need for specialized components for each pipeline, thereby limiting the increase in device complexity while maintaining high productivity.

The patent extracts the simple addition function from the complex FPGA logic and implements it using a dedicated unity addition module. This extraction allows the FPGA to focus its resources on complex logic functions while the simple, resource-intensive addition operation is handled by a specialized, efficient module, thereby reducing overall resource consumption in the FPGA.

The unity addition module acts as an intermediary between the FPGA and the pipeline modules. It handles the simple but resource-intensive addition operation externally to the FPGA logic, allowing the FPGA to maintain its adaptability for complex functions while avoiding direct resource consumption for the addition operation. This intermediary approach optimizes resource distribution between simple and complex functions.