Pixel Power Line Overlap Layout for Uniform Display Luminance
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Solution Overview
Problem
In display apparatuses, pixels with long wiring distances from the power supply circuit experience decreased potential due to wiring resistance, leading to reduced luminance and degraded display quality.
Innovation Solution
The display apparatus incorporates a pixel structure with transistors and conductive layers arranged in overlapping opening portions of insulating layers, allowing for efficient electrical connections to power and scan line driver circuits, enhancing display quality and resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the wiring distance from the power supply circuit is increased to expand display area, then the display area is improved, but the potential decreases due to wiring resistance
Solution Approach 1:
The patent introduces a second conductive layer that overlaps with the first conductive layer in the vertical dimension, creating parallel power supply paths. This dimensional transition from single-layer to multi-layer conductive structure enables simultaneous expansion of display area while maintaining power supply potential stability through reduced effective wiring resistance.
Solution Approach 2:
The patent implements nested conductive layers where the second conductive layer is positioned within the same planar footprint as the first conductive layer but at a different vertical level. This nesting arrangement allows multiple power supply paths to occupy the same spatial region, effectively reducing wiring resistance without increasing the overall display area footprint.
2Productivity
If transistor size is reduced to increase integration, then the degree of integration is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the transistor structure into multiple segmented conductive layers (first conductive layer, second conductive layer, third conductive layer) separated by insulating layers. This segmentation allows each layer to be optimized independently for specific functions while maintaining overall miniaturization, thereby increasing integration degree without excessively demanding manufacturing precision.
Solution Approach 2:
The patent employs composite material structures combining different conductive materials and insulating materials in layered configurations. This composite approach enables precise control of electrical characteristics and physical dimensions at the micro-scale, facilitating high integration while managing manufacturing precision requirements through material property optimization.
Data Source
AI summary
A display apparatus with high display quality is provided. The display apparatus includes a pixel, a scan line driver circuit, and a power supply circuit. The pixel includes first and second transistors, and in the second transistor, a semiconductor layer is provided in a first opening portion formed in an interlayer insulating layer over a substrate. A first conductive layer functioning as a gate electrode of the first transistor includes a region extending in a first direction and is electrically connected to the scan line driver circuit. A second conductive layer functioning as a source electrode or a drain electrode of the second transistor is provided over the interlayer insulating layer and includes a second opening portion overlapping with the first opening portion. The second conductive layer includes a region extending in a second direction perpendicular to the first direction and is electrically connected to the power supply circuit. The first conductive layer and the second conductive layer include a region where they overlap with each other with an insulating layer, which functions as a gate insulating layer of the first and second transistors and is provided in a layer between the first conductive layer, and the second conductive layer and the semiconductor layer, therebetween.