Pixel Power-Line Layout to Reduce IR Drop in OLED Displays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current display devices face challenges in efficiently managing power distribution and capacitance to achieve high-resolution, high-quality image display, particularly in the design and layout of power lines and capacitors within the pixel circuits.
Innovation Solution
The display device incorporates a specific layout with a first data line on a first interlayer insulating layer, first and second power lines on a second interlayer insulating layer, and a storage capacitor, where the power lines are connected to the pixel electrodes and transistors in a manner that minimizes IR drop and parasitic capacitance, with the second via hole being larger than the first via hole to facilitate efficient power transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power lines are routed through multiple interlayer insulating layers to reach pixel electrodes, then electrical connection is achieved, but IR drop and parasitic capacitance increase
Solution Approach 1:
The patent transitions from planar routing to three-dimensional vertical routing by placing power lines on different interlayer insulating layers (first and second interlayer insulating layers) at different heights. This vertical stacking allows power lines to reach pixel electrodes through via holes without excessive horizontal traversal, reducing resistance and parasitic capacitance while maintaining reliable electrical connection.
2Manufacturing precision
If via holes are made smaller to increase pixel density, then resolution improves, but power transfer efficiency decreases
Solution Approach 1:
The patent divides the via hole structure into multiple segments: first via holes connecting the first power line to intermediate structures, and second via holes connecting to the pixel electrode. This segmentation allows optimization of each via hole's dimensions independently, enabling smaller overall via holes for high pixel density while maintaining adequate cross-sectional area for power transfer through the stacked configuration.
3Loss of energy
If power lines are made wider to reduce resistance, then IR drop decreases, but pixel circuit area increases
Solution Approach 1:
The patent moves power line routing from the horizontal plane to the vertical dimension by utilizing multiple interlayer insulating layers. This allows power lines to be narrower in the horizontal direction (reducing pixel circuit area) while maintaining adequate cross-sectional area for low resistance through the vertical stacking configuration and multiple connection points via via holes.
4Loss of energy
If multiple interlayer insulating layers are used for power line routing, then power distribution is optimized, but device structure becomes more complex
Solution Approach 1:
The first and second interlayer insulating layers serve multiple functions: they provide electrical insulation between power lines and data lines, support vertical routing for power delivery, and enable the via hole connection structure. This multi-functionality reduces the need for additional dedicated insulation layers, optimizing power distribution while limiting the increase in structural complexity.
Data Source
AI summary
There is provided a display device. The display device includes a first data line on a first interlayer insulating layer over a substrate, a first power line and a second power line on a second interlayer insulating layer, the second interlayer insulating layer covering the first data line, and a plurality of pixels. A first pixel among the plurality of pixels includes a display element including a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode, the second power line being connected to the opposite electrode, and a driving thin film transistor between the substrate and the display element and including a driving semiconductor layer, a driving gate electrode, a driving source electrode, and a driving drain electrode, the first interlayer insulating layer covering the driving gate electrode, and the first power line being connected to the driving source electrode.