Pixel Circuit Pre-Charge Layout for Uniform Self-Luminous Displays
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Solution Overview
Problem
Display devices with self-luminous light-emitting elements face issues with display defects such as unevenness, which existing technologies have not adequately addressed.
Innovation Solution
The display device incorporates a specific configuration of transistors and capacitive elements, along with a controlled voltage supply system, to manage pixel luminance and gradation, using transistors with metal oxide semiconductor properties to minimize charge leakage and maintain pixel state stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional pixel circuit configuration is used, then the device complexity is low, but display uniformity deteriorates due to charge leakage and pixel state instability
Solution Approach 1:
The pixel circuit is divided into multiple functional blocks with distinct transistors (T1-T6) and capacitive elements (C1, C2) performing specific functions: data writing, threshold voltage compensation, pre-charge, and initialization. Each transistor is controlled by dedicated control signals (SC1-SC5) to manage charge flow independently, ensuring stable pixel states while maintaining display uniformity across the display panel.
Solution Approach 2:
The pre-charge transistor (T6) supplies a pre-charge voltage to the first node before the main data writing operation occurs. This preliminary action prepares the pixel circuit by establishing an initial charge state that prevents charge leakage during subsequent operations, thereby maintaining display uniformity without requiring excessive circuit complexity.
2Stability of the object's composition
If transistors with metal oxide semiconductor properties are used, then charge leakage is reduced and pixel state stability is improved, but device complexity increases
Solution Approach 1:
The patent utilizes transistors with metal oxide semiconductor properties, which have distinct electrical parameters compared to conventional transistors. These material parameter changes result in lower off-state current and reduced charge leakage, thereby improving pixel state stability. The specific transistor structure and material composition are optimized to achieve stable pixel operation while managing the increased circuit complexity through efficient layout and control signal management.
3Reliability
If multiple transistors and capacitive elements are added to manage pixel charge, then display uniformity is improved, but power consumption increases
Solution Approach 1:
The pixel circuit operates in periodic cycles with distinct phases: initialization phase where the initialization transistor (T5) resets the pixel state, pre-charge phase where transistor (T6) supplies charge, data writing phase where transistor (T1) writes data, and maintenance phase where the capacitive elements hold the charge. This periodic operation allows the circuit to maintain display uniformity through controlled charge management while minimizing power consumption by keeping transistors in off-state during maintenance periods.
Solution Approach 2:
The capacitive elements (C1, C2) in the pixel circuit serve to store and maintain the charge state autonomously once charged by the transistor network. This self-service function reduces the need for continuous power supply to maintain pixel states, thereby improving display uniformity over time while minimizing additional power consumption from the transistor circuitry.
Data Source
AI summary
A display device includes a first transistor controlled by a first control signal and connected between an image data signal line and a first node, a third transistor controlled by a second control signal and connected between the first node and a second node, a second transistor connected to the second node and connected between a power line and a third node, a fourth transistor controlled using a third control signal and connected between a reference voltage power line and the second node, a fifth transistor controlled by a fourth control signal and connected between an initialization voltage power line and the third node, and a sixth transistor controlled by a fifth control signal and connected between a pre-charge voltage power line and the first node.