Pixel Processing Pipeline CRC Checks for ASIL Memory Efficiency

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Solution Overview

Problem

Existing automotive systems face challenges in achieving high memory bandwidth efficiency while meeting Automotive Safety Integrity Level (ASIL) requirements due to the use of error checking and correction (ECC) mechanisms, which consume significant memory bandwidth.

Innovation Solution

Implementing in-line cyclic redundancy check (CRC) checksum computation at each stage of the processing pipeline to reduce memory traffic and ensure safety integrity, with CRC as the primary error detection and ECC as a secondary mechanism for specific triggers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error checking and correction (ECC) mechanisms are used to meet ASIL requirements, then safety integrity is improved, but memory bandwidth efficiency deteriorates

Engineering Contradiction:

Improvesafety integrityVSAvoidmemory bandwidth efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent segments the error detection function into two parts: CRC for primary error detection in normal operation, and ECC for secondary error correction when triggered. This segmentation allows the system to use the lighter CRC mechanism most of the time, improving memory bandwidth efficiency while maintaining safety integrity through the fallback ECC mechanism.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies partial error correction by using CRC checksums for the majority of error detection needs and only invoking full ECC mechanisms when CRC detects an error. This partial approach avoids the excessive bandwidth consumption of always-using ECC, while still providing adequate safety coverage through the combination of both mechanisms.

Inventive Principle:

Principle #16Partial or excessive action

2Productivity

If in-line CRC checksum computation is implemented at each pipeline stage, then memory bandwidth efficiency is improved, but system complexity increases

Engineering Contradiction:

Improvememory bandwidth efficiencyVSAvoidsystem complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the CRC computation function directly into the existing pixel processing pipeline stages, so that error detection is performed in-line with normal processing operations. This integration avoids adding separate error checking hardware blocks and reduces overall system complexity while maintaining memory bandwidth efficiency.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The processing pipeline components are designed to perform multiple functions: normal pixel processing and in-line CRC computation. This multi-functionality eliminates the need for dedicated error checking hardware, reducing system complexity while achieving the desired memory bandwidth efficiency through integrated error detection.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250258736A1Functionally safe pixel processing using efficient hardware integrity checks

Publication Date: 2025.08.14 RIVIAN HOLDINGS LLC

AI summary

Aspects of the disclosure relate to an integrated circuit that operates an approach for data processing pipeline using end to end hardware integrity checks that may be efficient in memory bandwidth utilization. An apparatus may use safety mechanisms with in-line CRC checksum computation on the sender or receiver side of each stage of the processing pipeline.