Pixel Circuit Using Q-Node Scan Driver to Reduce Display Dead Space
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Solution Overview
Problem
Display devices have dead spaces where images cannot be displayed due to the presence of drivers and lines in non-display areas, leading to inefficiencies in space utilization.
Innovation Solution
A pixel design incorporating multiple transistors that allow for the reduction of scan driver complexity and size by directly connecting transistors to a Q node, enabling a more compact scan driver layout, thereby reducing the non-display area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If drivers and lines are located in non-display area, then image display function is achieved, but dead space increases
Solution Approach 1:
The patent moves the scan driver from the non-display area (2D plane) into the display area by utilizing the third dimension (vertical stacking). The scan driver is formed beneath the pixel circuit in the same pixel region, transforming the spatial arrangement from horizontal separation to vertical integration, thereby eliminating dead space while maintaining display functionality.
Solution Approach 2:
The scan driver is nested within the pixel structure by placing it in the lower layer beneath the pixel circuit. This nested arrangement allows the scan driver to occupy the same footprint area as the pixel, effectively hiding the driver within the display region and eliminating the need for separate non-display area.
2Ease of operation
If scan driver is placed in non-display area, then scanning function is provided, but device complexity increases
Solution Approach 1:
The patent merges the scan driver with the pixel circuit by integrating them in a stacked configuration. The scan driver transistors and pixel circuit transistors are combined in the same vertical column, sharing common structures such as contact holes and conductive layers, thereby reducing overall device complexity despite adding functionality.
Solution Approach 2:
The lower layer structures serve dual purposes: they form part of the scan driver circuitry while simultaneously providing support structures for the upper pixel circuit. The same conductive layers and insulating layers are utilized by both the scan driver and pixel circuit, reducing the total number of separate components needed.
Data Source
AI summary
A pixel includes a first transistor including a first terminal configured to receive a driving voltage, a second terminal connected to a light-emitting diode, and a gate terminal connected to a node, a second transistor including a first terminal configured to receive a data voltage, a second terminal connected to the node, and a gate terminal configured to receive a scan signal, a third transistor including a first terminal configured to receive an initialization voltage, a second terminal connected to the light-emitting diode, and a gate terminal configured to receive a sensing signal, and a fourth transistor including a first terminal configured to receive a scan clock signal, a second terminal connected to the gate terminal of the second transistor, and a gate terminal configured to receive a voltage of a Q node.