Pixel Rate Timing Control for 2D Image Processing
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Solution Overview
Problem
Conventional 2-D image processing approaches face inefficiencies when transitioning to a new line or frame, requiring extra clock cycles or increased memory bandwidth to maintain a constant pixel output rate due to the need to fetch additional pixel data columns.
Innovation Solution
Implementing a timing control mechanism that fetches one new vector of pixel data from storage during each clock unit, and fills new vectors beyond the image edge with predetermined values, allowing for simultaneous fetching of pixel data from the next line or frame, thereby maintaining a constant memory fetch and pixel output rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 2-D image processing approaches are used with raster pattern convolution, then pixel blocks can be processed systematically, but extra clock cycles or increased memory bandwidth is required during line or frame transitions to maintain constant pixel output rate
Solution Approach 1:
The patent applies preliminary action by pre-fetching pixel data columns into a buffer memory before they are actually needed for convolution operations. During normal processing, the buffer is filled one column at a time in sync with the raster scan. During line or frame transitions, previously fetched columns are already available in the buffer, eliminating the need for extra clock cycles or increased memory bandwidth to maintain the constant pixel output rate.
2Speed
If the kernel is advanced to the next pixel during raster processing, then continuous processing can be maintained, but during line or frame transitions two new columns of pixel data need to be fetched which disrupts the one-to-one timing relationship
Solution Approach 1:
The patent pre-fetches pixel data columns into buffer memory in advance of when they are needed for convolution. During line or frame transitions, the buffer already contains the necessary columns, allowing the kernel to advance to the next pixel without waiting for additional column fetches. This maintains the one-to-one timing relationship between kernel advancement and pixel output, preventing loss of processing time.
Solution Approach 2:
The patent introduces a buffer memory as an intermediary between the image data storage and the convolution processing unit. This buffer acts as a mediator that decouples the timing between data fetching and processing operations. During transitions, the buffer provides the necessary pixel columns without requiring the processing to wait for additional memory access, thus maintaining continuous high-speed processing.
3Reliability
If memory bandwidth is increased to maintain constant pixel rate during transitions, then pixel output consistency is improved, but system resource consumption increases
Solution Approach 1:
The patent uses preliminary action by pre-fetching pixel data columns into a buffer memory during normal processing operations. This allows the buffer to be stocked with data before transitions occur, eliminating the need for increased memory bandwidth during line or frame transitions. The system maintains constant pixel output rate consistency while using the same memory bandwidth resources throughout operation.
Solution Approach 2:
The patent creates a copy of pixel data columns in the buffer memory, separate from the original image data storage. This copying allows the processing unit to access pixel columns from the buffer during transitions without requiring additional bandwidth from the original memory, thus maintaining output consistency without increasing overall memory bandwidth consumption.
Data Source
AI summary
Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.