CMOS Pixel Readout Transistor Layout for Lower Flicker Noise
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Solution Overview
Problem
Complementary metal-oxide semiconductor (CMOS) image sensors face poor noise performance due to the size reduction of pixel devices to accommodate full-depth deep trench isolation structures, leading to increased flicker noise and decreased accuracy and reliability of images.
Innovation Solution
The image sensor design includes a readout transistor that extends over the isolation structure between adjacent pixel sensors, functioning as two transistors in parallel, reducing effective channel resistance and parasitic capacitance, and increasing the effective length of the conductive channel to improve noise performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pixel device size is reduced to accommodate full-depth deep trench isolation structures, then electrical isolation between pixel sensors is improved, but noise performance deteriorates due to increased flicker noise
Solution Approach 1:
The readout transistor is designed to extend in the lateral dimension over the isolation structure, utilizing the third dimension (vertical stacking) to achieve both electrical isolation and adequate channel length. The transistor gate extends over the deep trench isolation structure, allowing the channel to span across multiple pixel sensor regions while maintaining proper isolation, thus resolving the contradiction between isolation requirements and noise performance.
Solution Approach 2:
The readout transistor channel is effectively segmented into multiple regions by extending over the isolation structure between adjacent pixel sensors. This segmentation allows the transistor to function as multiple parallel channels, reducing effective channel resistance and parasitic capacitance while maintaining adequate total channel length for low noise performance.
2Area of stationary object
If pixel device size is reduced, then device area is decreased allowing more pixels, but noise performance deteriorates due to shorter channel length
Solution Approach 1:
The readout transistor utilizes vertical stacking and lateral extension over the isolation structure to maintain adequate channel length while minimizing footprint area. By extending the gate over the deep trench isolation structure in the lateral direction, the design achieves both compact area and sufficient channel length for low noise performance.
Solution Approach 2:
Multiple pixel sensor regions are merged through the extended readout transistor that spans across the isolation structure. The transistor functions as parallel channels from multiple pixels, effectively combining their signals while maintaining adequate channel length through the lateral extension over the isolation structure.
3Object-affected harmful factors
If readout transistor channel length is increased to reduce noise, then noise performance is improved, but device area increases
Solution Approach 1:
The readout transistor achieves extended channel length by utilizing the vertical dimension and lateral extension over the isolation structure rather than simple planar expansion. The gate extends over the deep trench isolation structure, allowing the channel to lengthen in the lateral direction while maintaining a compact overall device footprint through efficient spatial utilization.
Data Source
AI summary
Various embodiments of the present disclosure are directed towards a method for forming an image sensor, the method includes forming a first photodetector and a second photodetector in a substrate. An isolation structure is formed in the substrate between the first photodetector and the second photodetector. A readout transistor is formed over the isolation structure. The readout transistor includes a first sidewall directly over the first photodetector and a second sidewall directly over the second photodetector. A height of the readout transistor from the first sidewall to the second sidewall is constant.