Pixel Structure with Recessed Insulating Layer for LCD Panels
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Solution Overview
Problem
The increasing number of gate and source drivers in LCD panels leads to expanded non-display regions, increasing manufacturing costs and reducing display quality due to excessive parasitic capacitance affecting pixel electrodes and signal charges.
Innovation Solution
A pixel structure is designed with a data line covered by a capacitor electrode line, reducing parasitic capacitance through recesses in insulating layers, which are connected to active devices and pixel electrodes, thereby alleviating signal interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of gate drivers and source drivers is increased to improve resolution, then the display resolution is improved, but the non-display region expands and manufacturing costs increase
Solution Approach 1:
The patent combines the function of the data line with the capacitor electrode line, allowing a single conductive structure to serve dual purposes: signal transmission and parasitic capacitance reduction. This merging eliminates the need for separate structures and reduces the overall space required in the non-display region.
Solution Approach 2:
The data line is designed to simultaneously function as a signal transmission line and as a capacitor electrode. This multi-functionality reduces the number of separate components needed, thereby reducing the non-display region area while maintaining display resolution.
2Measurement precision
If the number of gate drivers and source drivers is increased to improve resolution, then the display resolution is improved, but manufacturing costs increase
Solution Approach 1:
By merging the data line and capacitor electrode line into a single structure, the patent reduces the number of manufacturing steps and materials required, thereby lowering manufacturing costs while maintaining high display resolution.
Solution Approach 2:
The multi-functional data line reduces component count and simplifies the manufacturing process, leading to cost reductions without compromising the high resolution achieved through increased driver counts.
3Ease of operation
If the data line is disposed parallel to scan lines to simplify routing, then the routing is simplified, but parasitic capacitance between data line and pixel electrodes increases
Solution Approach 1:
The patent introduces an insulating layer as an intermediary between the data line and pixel electrodes. This insulating layer acts as a mediator that reduces parasitic capacitance while allowing the data line to maintain its parallel routing configuration for simplicity.
Solution Approach 2:
The patent extracts the harmful parasitic capacitance effect by introducing the insulating layer that separates the data line from the pixel electrodes, thereby removing the direct capacitive coupling while maintaining the simplified parallel routing arrangement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic capacitance, improving signal integrity and display quality while minimizing the non-display region, thus lowering manufacturing costs and allowing for narrower side frames.
Implementation Method 1
the impact on charges or signals of pixel electrodes caused by excessive parasitic capacitance between the pixel electrodes and data lines
Data Source
AI summary
A pixel structure includes a first and a second scan lines, a data line, a first insulating layer covering the first and the second scan lines and a portion of the data line and having a recess, a second insulating layer covering the first insulating layer, a capacitor electrode line covering the data line and the recess, a third insulating layer on the capacitor electrode line, a first active device electrically connected to the second scan line and the data line, a second active device electrically connected to the first active device and the first scan line, and a first and a second pixel electrodes electrically connected to the first and the second active devices, respectively. The portion of the data line and the first and the second scan lines are in the same layer. The recess is located at two sides of the portion of the data line.