Photoelectric Conversion Pixel With Reference Voltage Contact

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Solution Overview

Problem

As photoelectric conversion apparatuses increase in pixel density, pixel size decreases, leading to reduced light sensitivity and deteriorated image quality due to decreased light entry and variations in well potential, which existing technologies have not adequately addressed.

Innovation Solution

A photoelectric conversion apparatus is designed with a semiconductor substrate and regions of specific conduction types to include a high-concentration semiconductor region for supplying reference voltage, a low-concentration region, and a contact plug, which reduces shading and non-uniformity while maintaining pixel layout symmetry and moderating the electric field, thereby suppressing leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If pixels are made smaller to increase pixel density, then the number of pixels increases, but light sensitivity decreases and image quality deteriorates

Engineering Contradiction:
Improvepixel densityVSAvoidlight sensitivity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by creating a P-type semiconductor region specifically surrounding the N-type photoelectric conversion region. This localized doping structure concentrates the light-sensitive area while maintaining small pixel dimensions, allowing high pixel density without sacrificing sensitivity. The P-type region acts as a potential well that confines photogenerated carriers within the active photoelectric conversion zone.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the impurity concentration parameter by forming a P-type semiconductor region with specific doping levels around the N-type photoelectric conversion region. This parameter modification creates an internal electric field and potential well structure that enhances carrier collection efficiency, thereby improving light sensitivity even as pixel size decreases to increase density.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a contact is provided for each pixel to suppress shading, then shading due to well potential variations is suppressed, but chip area increases

Engineering Contradiction:
Improveshading suppressionVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the well potential control function with the pixel structure itself by forming a P-type semiconductor region that surrounds the N-type photoelectric conversion region. This integrated structure provides well potential stabilization without requiring separate contact structures for each pixel, thereby suppressing shading effects while maintaining compact chip area.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The P-type semiconductor region serves multiple functions simultaneously: it creates the potential well for carrier confinement, stabilizes the well potential to suppress shading, and defines the pixel boundary. This multi-functional structure eliminates the need for additional dedicated contacts, preventing chip area expansion while achieving shading suppression.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If pixels are made finer to increase density, then more pixels fit on the chip, but the amount of light entering each pixel decreases

Engineering Contradiction:
Improvepixel densityVSAvoidlight entry amount
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent enhances light utilization efficiency by creating a localized P-type semiconductor region that forms a potential well around the N-type photoelectric conversion region. This structure confines photogenerated carriers within the small pixel area, ensuring that even the limited light entering each fine pixel is efficiently converted and collected, thereby maintaining signal strength despite reduced light entry amount.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent modifies the electrical parameters of the pixel by introducing a P-type doped region with specific impurity concentration. This creates an internal electric field that enhances carrier separation and collection efficiency, allowing the pixel to maximize the use of incident light energy even as pixel size decreases and light entry amount reduces.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances image quality by reducing shading and leakage current, improving sensitivity and reducing image defects, and facilitating image correction while maintaining pixel layout symmetry and reducing memory requirements.

Implementation Method 1

a photoelectric conversion unit including a third semiconductor region of the first conduction type having an impurity concentration higher than the first semiconductor region and a fourth semiconductor region of the second conduction type

Methodology Applied
Scientific EffectPhotoelectric conversion: Photoelectric Effect

Data Source

PatentUS8415724B2Photoelectric conversion apparatus and imaging system using photoelectric conversion apparatus
Publication Date: 2013.04.09 CANON KK
  • US8415724B2 patent drawing
  • US8415724B2 patent drawing
  • US8415724B2 patent drawing

AI summary

A photoelectric conversion apparatus includes a photoelectric conversion unit with a semiconductor region of a first conduction type, an amplifying transistor, and a contact. The contact supplies, via a semiconductor region of a second conduction type arranged along a side surface and a bottom surface of an element isolation region, a reference voltage to the semiconductor region of the second conduction-type arranged below source and drain regions of the amplifying transistor in a region below a gate electrode of the amplifying transistor.