Image Capturing Device Pixel Row Capacitance Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing image capturing devices face challenges in expanding the dynamic range of signal output from pixels, particularly under high illumination levels, due to limitations in capacitance value adjustment at the input node of amplification transistors, leading to saturation issues and reduced signal-noise ratios.
Innovation Solution
The implementation of a configuration where at least two pixel rows, each with a switch and a capacitor, are arranged in a column direction, allowing the capacitance value at the input node of amplification transistors to be dynamically changed by a buffer-driven switch, thereby adjusting the charge-voltage conversion efficiency and enhancing the dynamic range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a capacitor is connected to an input node of an amplification transistor to increase dynamic range, then the dynamic range is improved, but the device complexity increases due to additional components and control circuits
Solution Approach 1:
The patent merges the drive lines for switches in different pixel rows by making them electrically connected through a common node. This allows multiple pixel rows to share the same drive line, reducing the total number of drive lines needed and simplifying the overall device structure while maintaining the dynamic range enhancement capability
Solution Approach 2:
The common node serves multiple functions: it acts as the output node for the buffer and simultaneously as the input node for multiple switches across different pixel rows. This multi-functional design reduces the number of separate control circuits needed, thereby reducing device complexity while preserving adaptability
2Measurement precision
If separate drive lines are provided for each pixel row to control switches, then the control precision is improved, but the device complexity increases due to more drive lines and buffers
Solution Approach 1:
The patent combines multiple drive lines into a single common drive line that serves multiple pixel rows. The switches in different pixel rows are controlled through this shared drive line, reducing the number of separate control circuits while maintaining synchronized control precision across all connected pixels
Solution Approach 2:
The patent introduces a new dimensional approach by arranging pixel rows such that switches from different rows can share a common control node. This spatial reorganization allows multiple rows to be controlled through a single drive line, reducing complexity without sacrificing control precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the likelihood of saturation under high illumination and increases the signal-noise ratio by allowing for a larger voltage amplitude conversion, thereby improving the dynamic range and image capturing capabilities.
Implementation Method 1
each pixel of the plurality of pixels including a photoelectric conversion unit
Data Source
AI summary
An image capturing device includes a pixel unit and a buffer. In the pixel unit, pixels are arranged in a matrix, wherein each pixel includes a photoelectric conversion unit, a transfer transistor, and an amplification transistor. In the pixel unit, first and second pixel rows are arranged in a column direction. A first pixel row first pixel includes a first switch that changes a capacitance value at an input node of an amplification transistor included in the first pixel. A second pixel row second pixel includes a second switch that changes a capacitance value at an input node of an amplification transistor included in the second pixel. The buffer drives the first and second switches. A buffer output node is electrically connected to a first switch input node and a second switch input node to be common to the first switch input node and the second switch input node.