Pixel Scan Timing for Lower-Power Display Circuits

The patent applies dynamic control to the pixel circuit by implementing multiple operational modes (first mode with first frequency, second mode with second frequency less than first frequency) that can be switched based on display requirements. The circuit dynamically adjusts its operation by applying different scan signals to different transistors during different time periods, allowing the system to optimize power consumption while maintaining display functionality.

The patent implements periodic action through the use of frame periods that are divided into multiple time periods within each frame. Scan signals are applied periodically to different transistors (first transistor, second transistor, third transistor, fourth transistor, fifth transistor, sixth transistor) at specific time intervals, creating a rhythmic pattern of charging and discharging that reduces unnecessary power consumption while maintaining display operation.

The patent segments the continuous scanning process into distinct time periods within each frame period. Each time period is assigned to scan specific transistors (first scan line, second scan line, third scan line, fourth scan line, fifth scan line, sixth scan line) sequentially rather than continuously scanning all transistors simultaneously. This segmentation allows the display to maintain refresh functionality while reducing the overall power consumption by activating only the necessary scanning operations at each time period.

The patent implements a scanning strategy where certain transistors are scanned and charged during specific time periods, then allowed to discharge or maintain their state during subsequent periods. The first capacitor charges during certain time periods and then maintains or discharges during others, effectively discarding unnecessary charging operations and recovering power by allowing capacitors to maintain their charge states without continuous replenishment.