Pixel Sensor Hierarchical Memory Architecture
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Solution Overview
Problem
Current image sensors face challenges in reducing the size and power consumption of pixel cells, which affects the number of pixel cells that can be fit into an array, leading to limitations in resolution and performance, especially in applications where space and power are limited, such as in mobile and wearable devices.
Innovation Solution
The implementation of an image sensor with an array of pixel cells that includes an off-array frame memory for temporary storage of pixel values, reducing the capacity and footprint of in-pixel memory, and using parallel interconnects for faster data transfer, allowing for simultaneous processing and transfer of data to a host device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If in-pixel memory capacity is increased to store digital outputs, then data storage capability is improved, but pixel cell size and power consumption increase
Solution Approach 1:
The memory system is segmented into two parts: small in-pixel memory within each pixel cell for immediate digital output storage, and large off-chip frame memory for bulk data storage. This segmentation allows the pixel cell to maintain small size while the system achieves large total storage capacity through the distributed memory architecture.
Solution Approach 2:
The patent moves memory storage from the two-dimensional pixel plane to the third dimension by using off-chip frame memory connected through vertical interconnects (TSVs). This dimensional transition allows large storage capacity without increasing the lateral pixel cell area, as memory is stacked vertically below or above the pixel array.
2Quantity of substance
If in-pixel memory capacity is increased to store digital outputs, then data storage capability is improved, but power consumption increases
Solution Approach 1:
The memory system is segmented into two parts: small in-pixel memory within each pixel cell for immediate digital output storage, and large off-chip frame memory for bulk data storage. This segmentation allows the pixel cell to maintain small size while the system achieves large total storage capacity through the distributed memory architecture.
Solution Approach 2:
The patent introduces parallel interconnect structures (such as TSVs and copper-copper bumps) as intermediaries to transfer data between the pixel array and frame memory. These high-speed parallel interconnects reduce the time data remains in high-power states during transfer, thereby reducing overall power consumption compared to sequential transfer methods.
3Speed
If parallel interconnects are used for data transfer, then data transfer speed is improved, but device complexity increases
Solution Approach 1:
The parallel interconnect structures (TSVs and copper-copper bumps) serve multiple functions: they provide high-speed data transfer pathways, act as electrical connections between stacked layers, and enable both read and write operations to the frame memory. This multi-functionality reduces the need for separate dedicated structures for each function, thereby managing complexity.
Solution Approach 2:
The patent moves memory storage from the two-dimensional pixel plane to the third dimension by using off-chip frame memory connected through vertical interconnects (TSVs). This dimensional transition allows large storage capacity without increasing the lateral pixel cell area, as memory is stacked vertically below or above the pixel array.
4Measurement precision
If more pixel cells are packed into the array, then resolution is improved, but available space per pixel cell decreases
Solution Approach 1:
The patent extracts the large-capacity frame memory from the pixel cell area and places it off-chip, connected through parallel interconnects. This extraction removes the bulk storage requirement from the pixel cell footprint, allowing pixel cells to be packed more densely while maintaining sufficient total memory capacity for high-resolution imaging.
Solution Approach 2:
The patent moves memory storage from the two-dimensional pixel plane to the third dimension by using off-chip frame memory connected through vertical interconnects (TSVs). This dimensional transition allows large storage capacity without increasing the lateral pixel cell area, as memory is stacked vertically below or above the pixel array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the number of pixel cells that can be included, improving resolution, reducing power consumption, and enhancing the achievable frame rate and global shutter operation, while also supporting noise reduction and post-processing operations like correlated double sampling.
Implementation Method 1
a photodiode to generate a charge in response to incident light
Data Source
AI summary
In one example, an apparatus comprises an array of pixel cells, each pixel cell including: a photodiode to generate a charge in response to incident light, a charge sensing unit configured to generate a voltage based on the charge, a quantizer configured to generate a digital output based on quantizing the voltage, and an in-pixel memory configured to store the digital output. The apparatus further includes a bus interface, an off-array frame memory, and a frame memory controller configured to: control the frame memory to receive, via the set of parallel interconnects, the digital outputs from the in-pixel memory of each pixel cell of the array of pixel cells; store the digital outputs in the frame memory; fetch the digital outputs from the frame memory; and transmit the digital outputs to a host device via the bus interface.