3D Integrated Pixel Shielding Floating Diffusion Capacitance
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Solution Overview
Problem
CMOS image sensing devices face increased signal noise and reduced dynamic range due to increased floating diffusion capacitance in shared pixel designs and 3D wafer integration, leading to electrical crosstalk and parasitic capacitance issues.
Innovation Solution
A metal shield surrounds the wire interconnecting the floating diffusion on the sensor wafer with transistors on the circuit wafer, connected to an amplifier with gain greater than zero, reducing floating diffusion capacitance and minimizing electrical crosstalk by following the voltage on the floating diffusion node.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a shared pixel design is used to increase photodiode area, then photodiode capacity increases, but floating diffusion capacitance increases leading to reduced voltage-to-charge conversion ratio and increased read noise
Solution Approach 1:
A shielding wire is introduced as an intermediary element between the floating diffusion wire and surrounding structures. This shield acts as a mediator that reduces parasitic capacitance effects without changing the fundamental shared pixel architecture, thereby maintaining photodiode capacity while improving voltage-to-charge conversion ratio
Solution Approach 2:
The invention changes the electrical parameters of the floating diffusion node by introducing a shield that modifies the capacitive environment. By adjusting the shield's connection point (to the floating diffusion wire or directly to the amplifier), the effective capacitance is reduced, improving the voltage-to-charge conversion ratio while maintaining the shared pixel design benefits
2Quantity of substance
If 3D wafer integration is used to increase photodiode area, then photodiode capacity increases, but parasitic floating diffusion capacitance increases due to interconnect wires between wafers
Solution Approach 1:
The shielding wire serves as an intermediary that isolates the floating diffusion wire from parasitic capacitance sources in the 3D integrated structure. By placing the shield around the interconnect wire and connecting it to appropriate reference nodes, the harmful parasitic effects are reduced while maintaining the 3D integration benefits for increased photodiode area
3Area of stationary object
If floating diffusion wires are interconnected in parallel in shared pixel design, then photodiode area increases, but electrical crosstalk increases between adjacent floating diffusions
Solution Approach 1:
The shield acts as a protective intermediary around the floating diffusion wire, reducing capacitive coupling between adjacent wires. This allows parallel interconnection of multiple floating diffusions for increased photodiode area while minimizing electrical crosstalk through the shielding effect
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces floating diffusion capacitance and electrical crosstalk, enhancing the voltage-to-charge conversion ratio and improving the dynamic range of the image sensor.
Implementation Method 1
Feedback can be used to effectively reduce floating diffusion capacitance. The shielding wire is electrically connected to the output of the source follower amplifier. Because the signal of output follows the voltage on the floating diffusions with almost unity gain, the voltage on the shield follows the voltage on the floating diffusion.
Implementation Method 2
A metal shield surrounds the wire interconnecting the floating diffusion on the sensor wafer with transistors on the circuit wafer... minimizing electrical crosstalk by following the voltage on the floating diffusion node.
Data Source
Figure 1
Figure 2
Figure 3a~3b
AI summary
An image sensor includes (a) a first wafer having (i) a photosensitive area; (ii) a charge-to-voltage conversion region; (b) a second wafer having (i) a first amplifier that receives a signal from the charge-to-voltage conversion region; (c) an electrical interconnect connecting the charge-to-voltage conversion region to an input of the amplifier; (d) an electrically biased shield at least partially enclosing at least a portion of the electrical interconnect.