Pixel Shielding Layer Layout for TFT Parasitic Capacitance Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing number of thin film transistors (TFTs) in display devices leads to a higher number of wirings required for signal transfer, which complicates the control of light emission and can result in issues such as parasitic capacitance and off-current, affecting display quality.
Innovation Solution
The display device incorporates a shielding layer between the first electrode layer and the pixel electrode, which overlaps the node connection line and is connected to a constant or driving voltage. This configuration reduces parasitic capacitance and off-current by preventing voltage drops and external light interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of TFTs and wirings is increased to accurately control light emission, then the control precision is improved, but the device complexity and parasitic capacitance increase
Solution Approach 1:
A shielding layer is introduced as an intermediary component between the node connection line and the pixel electrode. This shielding layer acts as a mediator to block parasitic capacitance coupling and external light interference, thereby improving control precision without requiring additional TFTs or wirings that would increase device complexity.
Solution Approach 2:
The harmful parasitic capacitance effect is extracted and isolated by introducing the shielding layer. The shielding layer specifically targets and eliminates the parasitic capacitance between the node connection line and pixel electrode, separating this harmful effect from the main control circuitry and allowing precise control without the need for additional control elements.
2Measurement precision
If the number of TFTs and wirings is increased to accurately control light emission, then the control precision is improved, but the parasitic capacitance and off-current increase
Solution Approach 1:
The shielding layer serves as an intermediary that blocks the generation of parasitic capacitance between the node connection line and pixel electrode. By placing this conductive shielding layer connected to a fixed potential, the patent prevents capacitive coupling that would otherwise generate harmful parasitic effects, thereby maintaining control precision without increasing off-current.
Solution Approach 2:
The shielding layer is positioned in advance to prevent the formation of parasitic capacitance before it can affect the pixel operation. This preliminary protective structure counteracts the harmful capacitive coupling effect before it influences the light emission control, eliminating the need for additional TFTs that would otherwise be required to compensate for such effects.
3Reliability
If a shielding layer is added to reduce parasitic capacitance, then the display quality is improved, but the device complexity increases
Solution Approach 1:
The shielding layer is designed to perform multiple functions simultaneously: it blocks parasitic capacitance between the node connection line and pixel electrode, shields against external light interference, and maintains electrical potential stability. This multi-functionality allows the patent to improve display quality and reliability without adding proportionally more complex structures, as one component achieves multiple protective goals.
Solution Approach 2:
The shielding layer is merged with the existing electrode structure and integrated into the pixel architecture. Rather than being a completely separate component, the shielding layer is combined with the node connection line and pixel electrode structure, allowing it to reduce parasitic capacitance and improve display quality while minimizing the increase in overall device complexity through structural integration.
Data Source
AI summary
A display device includes: a plurality of pixels each including a driving thin film transistor and a storage capacitor, wherein each of the pixels further includes: a driving semiconductor layer including a driving channel region, a driving source region, and a driving drain region; a first electrode layer, a portion of the first electrode layer overlapping the driving channel region; a second electrode layer overlapping the first electrode layer; a node connection line having a first side connected to the first electrode layer; a pixel electrode overlapping the first electrode layer and the second electrode layer; and a shielding layer between the first electrode layer and the pixel electrode and overlapping the first electrode layer, the node connection line, and the pixel electrode.