Pixel Circuit Stacked Capacitors Reduce Parasitic Coupling
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Solution Overview
Problem
Current display devices face challenges in achieving improved display quality due to limitations in the design and integration of transistors and capacitors within the pixel circuit, which affect the overall performance and efficiency of the display panel.
Innovation Solution
The proposed display device incorporates a specific configuration of transistors and capacitors, including a light-emitting diode, switching transistors, driving transistors, and capacitors connected between voltage lines, with a detailed layering and electrical connection scheme that optimizes the operation of each pixel, utilizing metal oxide semiconductor regions and conductive patterns to enhance electrical connections and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If transistors and capacitors are integrated within the pixel circuit, then device complexity is reduced, but manufacturing precision and electrical connection quality deteriorate due to limited space and overlapping structures
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking by placing capacitors between different substrate layers (first substrate, second substrate, and third substrate). This vertical arrangement eliminates lateral interference and improves manufacturing precision by separating conductive patterns into different z-heights, allowing precise electrical connections through contact holes while maintaining compact pixel circuit integration.
2Area of stationary object
If conductive patterns are overlapped to save space, then area efficiency improves, but parasitic capacitance increases affecting signal stability
Solution Approach 1:
The patent introduces insulating layers as intermediary barriers between overlapped conductive patterns. These insulating layers electrically isolate conductive patterns that would otherwise be in direct contact, preventing parasitic capacitance formation while allowing the conductive patterns to maintain their overlapping spatial arrangement for area efficiency. The insulating layers act as mediators that enable close spacing without harmful electrical coupling.
3Reliability
If multiple capacitors are added to improve signal stability, then reliability improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent designs capacitors to serve multiple functions simultaneously. Each capacitor structure integrates both signal storage and decoupling capabilities, with capacitors positioned to stabilize signals from multiple data lines (first data line, second data line, third data line) while also providing local decoupling power supply functions. This multi-functionality reduces the need for separate dedicated components, maintaining reliability while controlling device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the display quality by optimizing the electrical connections and reducing parasitic capacitance, leading to more stable and efficient operation of the display panel, with enhanced luminance consistency across pixels.
Implementation Method 1
a light-emitting diode including a first electrode electrically connected to a first node, a second electrode which receives a first power voltage, and a light-emitting layer disposed between the first electrode and the second electrode
Data Source
AI summary
A pixel includes a driving transistor, a switching transistor, and first and second capacitors. The gate of the driving transistor is disposed below a first insulating layer, and a first conductive pattern defining a first electrode of the first capacitor is disposed below the first insulating layer. A second conductive pattern defining a second electrode of the first capacitor and a first electrode of the second capacitor is disposed on the first insulating layer, a third conductive pattern defining a second electrode of the second capacitor is disposed on a second insulating layer covering the second conductive pattern, and the data line is disposed above the second insulating layer.