Pixel Structure Fabrication Using Four Mask Steps
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Solution Overview
Problem
The conventional manufacturing process for pixel structures in displays requires a large number of mask steps, leading to increased fabrication time, defects, and reduced yield, as well as higher costs.
Innovation Solution
A method that reduces the number of mask process steps by using a sequence of conductive and dielectric layer formations, where two mask steps employ the same mask, allowing for the formation of a pixel structure with only four mask steps, thereby reducing fabrication costs and increasing throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If five mask process steps are used to manufacture pixel structure, then manufacturing precision can be maintained, but fabrication time increases and productivity decreases
Solution Approach 1:
The patent combines multiple patterning operations into fewer mask steps. Specifically, the source/drain electrode and pixel electrode are formed in a single mask step, and the semiconductor layer patterning is integrated with the dielectric layer patterning. This merging of operations reduces the total mask steps from five to four while maintaining the required patterning precision for each component.
Solution Approach 2:
The patent makes masks serve multiple functions. The first mask is reused for both gate electrode patterning and semiconductor layer patterning. The second mask simultaneously defines both the source/drain electrode and pixel electrode patterns. This multi-functionality reduces the total number of masks needed and accelerates the fabrication process.
2Manufacturing precision
If five mask process steps are used, then complete pattern definition is achieved, but fabrication cost increases
Solution Approach 1:
The patent merges the patterning of source/drain electrode and pixel electrode into a single mask step using the second mask. It also combines gate electrode patterning and semiconductor layer patterning into one mask step using the first mask. This reduction from five to four mask steps directly lowers fabrication costs while maintaining complete pattern definition for all components.
Solution Approach 2:
The first mask serves dual purposes: defining the gate electrode pattern and defining the semiconductor layer pattern. The second mask simultaneously defines both source/drain and pixel electrode patterns. This multi-functional use of masks reduces the total mask count and associated costs while ensuring all necessary patterns are correctly formed.
3Manufacturing precision
If five mask process steps are used, then all layers are properly patterned, but number of process steps increases leading to more defects
Solution Approach 1:
The patent combines multiple patterning functions into fewer mask steps. The first mask handles both gate and semiconductor layer patterning, while the second mask handles both source/drain and pixel electrode patterning. This reduction in process steps from five to four minimizes the opportunities for defects to occur during masking operations, thereby improving yield while maintaining patterning accuracy.
Solution Approach 2:
By making masks multi-functional (first mask for gate and semiconductor, second mask for source/drain and pixel electrode), the patent reduces the total number of masking operations. Fewer mask steps mean fewer opportunities for alignment errors, mask defects, and process variations, thus improving reliability and yield while maintaining the required patterning precision.
Data Source
AI summary
A method for manufacturing a pixel structure includes forming a first conductive layer on a substrate and patterning the first conductive layer with use of a first mask as an etching mask to form a gate. A dielectric layer is formed over the substrate to cover the gate. A semiconductor material layer is formed on the dielectric layer and patterned with use of the first mask as an etching mask to form a semiconductor layer on the dielectric layer. A second conductive layer is formed over the substrate and patterned with use of a second mask as an etching mask to form a source/drain over the substrate. A third conductive layer is formed over the substrate and patterned with use of a third mask as an etching mask to form a pixel electrode over the substrate. The pixel electrode is electrically connected to the drain.