Pixel Structure Fabrication Using Half-Tone Masking
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Solution Overview
Problem
The conventional pixel structure fabrication process requires a complex five-mask process, leading to increased manufacturing costs, defects, and reduced yield due to its time-consuming and complicated nature.
Innovation Solution
A method using fewer masks, specifically employing half-tone or gray-tone masks for patterning layers, and ion doping processes to form a pixel structure with a transistor having a gate at the bottom, which reduces manufacturing costs and defects while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional five-mask process is used to fabricate the pixel structure, then the manufacturing process can be completed with standard procedures, but the process becomes complicated and time-consuming, leading to increased manufacturing costs and reduced yield
Solution Approach 1:
The patent combines multiple patterning operations into a single exposure step by using a multi-layer mask structure. The first mask layer defines transistor patterns while the second mask layer defines pixel electrode patterns, allowing both to be formed simultaneously through one exposure process rather than separate masking steps.
Solution Approach 2:
The multi-layer mask structure serves multiple functions: it acts as a patterning mask for both transistor and pixel electrode regions, provides etch selectivity through different material layers, and enables sequential pattern formation without removing the mask between steps. This universal mask replaces what would traditionally require multiple separate masks.
2Manufacturing precision
If a conventional five-mask process is used to fabricate the pixel structure, then each layer can be patterned with dedicated masks, but the number of masks increases, leading to higher manufacturing costs
Solution Approach 1:
The patent merges the functions of multiple masks into a single multi-layer mask structure. The first mask layer and second mask layer work together to define both transistor patterns and pixel electrode patterns in one exposure step, eliminating the need for multiple separate masks and reducing mask-related costs.
Solution Approach 2:
The patent changes the material parameters of the mask layers to achieve different etch selectivities. By selecting materials with appropriate etch rate differences, the process can selectively remove portions of underlying layers without affecting other regions, maintaining patterning precision while using fewer masks.
3Manufacturing precision
If a conventional five-mask process is used to fabricate the pixel structure, then all necessary patterns can be formed, but the time lapse increases, leading to fixed cost increases from machines and equipment
Solution Approach 1:
The patent combines multiple patterning steps into a single exposure operation using a multi-layer mask. Both transistor patterns and pixel electrode patterns are defined simultaneously in one exposure step, significantly reducing the total fabrication time compared to sequential masking operations.
Solution Approach 2:
The multi-layer mask structure is prepared in advance with pre-defined pattern regions. The first mask layer is configured to define transistor patterns while the second mask layer defines pixel electrode patterns, allowing both to be formed in a single exposure step without intermediate mask changes or realignments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces manufacturing costs and defects, enhances transistor performance, and improves product yield by simplifying the fabrication process and incorporating an etching stop layer design.
Implementation Method 1
the stacked layer is patterned by using a first half-tone mask or a gray-tone mask
Implementation Method 2
a source/drain region of the transistor pattern is doped with use of a second half-tone mask or the gray-tone mask
Data Source
AI summary
A method for fabricating a pixel structure includes providing a substrate having a pixel area. A first metal layer, a gate insulator and a semiconductor layer are formed on the substrate and patterned by using a first half-tone mask or a gray-tone mask to form a transistor pattern, a lower capacitance pattern and a lower circuit pattern. Next, a dielectric layer and an electrode layer both covering the three patterns are sequentially formed and patterned to expose a part of the lower circuit pattern, a part of the lower capacitance pattern and a source/drain region of the transistor pattern. A second metal layer formed on the electrode layer and the electrode layer are patterned by using a second half-tone mask or the gray-tone mask to form an upper circuit pattern, a source/drain pattern and an upper capacitance pattern. A portion of the electrode layer constructs a pixel electrode.