Flat Panel Pixel Structure Lithography Reduction
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Solution Overview
Problem
The manufacturing process of low temperature polysilicon type flat panel displays requires complex and costly lithography processes, leading to increased costs and reduced capacitance of the storage capacitor due to the need for multiple lithography steps and the inability of semiconductor layers to serve as capacitor electrodes.
Innovation Solution
A pixel structure for flat panel displays is developed, where the upper metal layer and gate electrode are formed by the same metal layer, and the lower metal layer and data line are formed by the same metal layer, reducing the number of lithography steps and allowing a thinner insulating layer to be used as a capacitor dielectric, thereby increasing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple lithography steps are used to form separate metal layers and semiconductor layers, then the pixel structure can be formed with proper functionality, but the manufacturing process becomes complex and costly
Solution Approach 1:
The patent combines the formation of the lower metal layer and data line into a single lithography step by using the same metal layer material for both components. Similarly, the upper metal layer and gate electrode are formed using the same metal layer deposition and patterning process. This merging of processes reduces the total number of lithography steps from six to four, simplifying manufacturing while maintaining proper pixel functionality.
Solution Approach 2:
The metal layer material serves multiple functions simultaneously: it forms the lower metal layer that also acts as the data line, and the same material forms the upper metal layer that also serves as the gate electrode. This multi-functionality eliminates the need for separate lithography steps for each component, reducing process complexity while ensuring proper electrical connections and device operation.
2Reliability
If a thicker insulating layer is used as capacitor dielectric layer, then the storage capacitor can be formed, but the capacitance is reduced
Solution Approach 1:
The patent changes the thickness parameter of the insulating layer (second insulating layer) to a thinner configuration compared to conventional designs. By reducing the dielectric layer thickness while maintaining proper electrical insulation and capacitor functionality, the capacitance value increases. This parameter optimization allows the storage capacitor to achieve higher capacitance without compromising structural integrity or electrical performance.
Data Source
AI summary
A pixel structure of a flat panel display for arrangement on a substrate. The pixel structure comprises a storage capacitor, a thin film transistor (TFT) and a data line formed on the substrate. The storage capacitor is disposed on the substrate, comprising a lower metal layer, an upper metal layer and a capacitor dielectric layer disposed therebetween. The TFT is disposed on the substrate and electrically connected to the storage capacitor, comprising an active layer, a gate electrode, and a gate dielectric layer disposed therebetween. The data line is disposed on the substrate, electrically connected to the thin film transistor and insulated from the substrate. The upper metal layer and the gate electrode are formed by the same metal layer and the lower metal layer and the data line are formed by the same metal layer. The invention also discloses a method for fabricating the pixel structure.