Pixel Structure Reducing Parasitic Capacitance via Layered Insulation
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Solution Overview
Problem
The existing thin film transistor liquid crystal display pixel structures suffer from parasitic capacitance between the common electrode line and the data line, which increases the load on the data line and is unfavorable for the driving of the thin film transistor array, and the manufacturing process is complex with multiple photo-lithography and etching steps.
Innovation Solution
A pixel structure is designed with a substrate, scan line, data line, first and second insulating layers, active device, common electrode, and pixel electrode, where the data line has a linear and cross-line transmitting part, and the second insulating layer with an etching blocking pattern and isolation pattern reduces capacitive coupling between the data line and common electrode, using multiple insulating layers to space the common electrode from the data line, thereby reducing parasitic capacitance and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the common electrode line and data line are disposed on the same layer to reduce area, then the occupied area of metal conductive components is reduced, but parasitic capacitance increases between the overlapping lines
Solution Approach 1:
The patent moves the data line from the same layer as the common electrode line to a different layer (either above or below), utilizing the third dimension (vertical stacking) to resolve the conflict between area reduction and parasitic capacitance reduction. This allows the lines to overlap in the planar view for area efficiency while being separated vertically to minimize capacitance.
Solution Approach 2:
The patent introduces an insulating layer as an intermediary between the common electrode line and data line when they overlap. This insulating layer acts as a mediator that reduces the direct capacitive coupling between the two conductive lines while allowing them to occupy the same planar space.
2Manufacturing precision
If multiple photo-lithography and etching steps are used to form separate layers for gate electrode, scan line, source electrode, drain electrode and data line, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the formation of the data line with the formation of other conductive elements (gate electrode, scan line, source electrode, or drain electrode) into a single conductive layer. This merging reduces the number of separate photo-lithography and etching steps required, simplifying the manufacturing process while maintaining the necessary electrical connections and functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance, decreases power consumption, and simplifies the manufacturing process by using multiple insulating layers to isolate the common electrode from the data line, improving the efficiency and cost-effectiveness of the pixel structure.
Implementation Method 1
the second insulating layer with an etching blocking pattern and isolation pattern reduces capacitive coupling between the data line and common electrode
Data Source
AI summary
A pixel structure and a manufacturing method thereof are provided. The pixel structure includes a substrate, a scan line, a data line, a first insulating layer, an active device, a second insulating layer, a common electrode and a first pixel electrode. The data line crossed to the scan line is disposed on the substrate and includes a linear transmitting part and a cross-line transmitting part. The first insulating layer covering the scan line and the linear transmitting part is disposed between the scan line and the cross-line transmitting part. The active device, including a gate, an oxide channel, a source and a drain, is connected to the scan line and the data line. The second insulating layer is disposed on the oxide channel and the linear transmitting part. The common electrode is disposed above the linear transmitting part. The first pixel electrode is connected to the drain.