Pixel Substrate Fabrication Using Etching-Barrier Mask
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Solution Overview
Problem
The existing pixel structure fabrication for FFS LCDs is time-consuming and costly due to the need for eight mask processes.
Innovation Solution
A fabrication method that simplifies the process by forming an etching-barrier material layer to overlay the channel and first electrode layers, allowing for simultaneous patterning of the etching-barrier and gate insulating layers, reducing the number of mask processes and fabrication time, and using a second electrode layer with slits to overlap with the first electrode layer for electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If eight mask processes are used for fabricating the pixel structure, then the electrical connections and patterns can be formed with high precision, but the fabrication time increases and production cost becomes high
Solution Approach 1:
The patent combines multiple patterning operations into a single etching step. Specifically, the etching-barrier pattern layer is used as a mask to simultaneously pattern both the etching-barrier material layer and the gate insulating layer, forming contact openings through one etching process rather than requiring separate mask and etch steps for each layer.
Solution Approach 2:
The etching-barrier pattern layer serves multiple functions: it acts as an etching mask for patterning the etching-barrier material layer, serves as a protective layer during gate insulating layer removal, and defines the contact opening patterns. This multi-functional use of a single patterned layer eliminates the need for multiple dedicated mask layers.
2Manufacturing precision
If eight mask processes are used for fabricating the pixel structure, then the electrical connections can be established accurately, but the production cost becomes high
Solution Approach 1:
The patent merges multiple mask processes into fewer steps by using the etching-barrier pattern layer as a universal mask for patterning both the etching-barrier material layer and the gate insulating layer, reducing the total number of mask processes from eight to a smaller number while maintaining connection accuracy.
Solution Approach 2:
The etching-barrier pattern layer is designed to serve its own purpose as an etching mask while also protecting underlying layers during subsequent etching steps. This self-service capability eliminates the need for additional sacrificial mask layers and simplifies the manufacturing process.
3Manufacturing precision
If multiple separate patterning steps are used for the etching-barrier layer and gate insulating layer, then each layer can be patterned independently with high precision, but the number of patterning steps increases
Solution Approach 1:
The patent performs simultaneous patterning of the etching-barrier material layer and the gate insulating layer in a single etching step using the etching-barrier pattern layer as the mask. This combined patterning operation maintains the precision of individual layer patterning while doubling the fabrication efficiency by eliminating redundant mask and etch cycles.
Data Source
AI summary
A pixel substrate and a fabrication method thereof are provided. The method includes: forming a gate and a lower pad on a substrate; forming a gate insulating layer overlaying the gate and the lower pad; forming a channel layer and a first electrode layer on the gate insulating layer, in which the projection areas of the channel layer and the gate on the substrate are overlapped; forming an etching-barrier material layer on the substrate and simultaneously forming a contact opening at the gate insulating layer to expose the lower pad; forming a source, a drain and an upper pad on the substrate; forming a protective layer; forming a second electrode layer with multiple slits on the protective layer, in which one of the first and second electrode layers is electrically connected to the drain. The invention can simplify the process steps and reduce fabrication time.