Pixel Circuit Test Mode for Transistor Defect Detection

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Solution Overview

Problem

Existing display devices face reliability issues due to the inability to effectively test and isolate defects in the transistors within pixels, leading to potential short circuits and reduced performance.

Innovation Solution

A pixel structure is introduced with a specific configuration of transistors and capacitors, including a tenth transistor that allows for a comprehensive test mode to apply a test voltage, enabling thorough testing of all transistors and improving defect detection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional pixel structure without comprehensive test capability is used, then the device complexity is reduced, but the reliability deteriorates due to inability to detect transistor defects

Engineering Contradiction:
Improvetransistor defect detectabilityVSAvoidpixel circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The pixel circuit performs preliminary testing of all transistors during the initialization period before normal operation begins. The test mode activates all transistors including the eleventh transistor to verify their functionality, allowing defects to be detected before they can cause display failures during actual image rendering.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The pixel circuit is designed with multi-functionality by incorporating test modes that can activate all transistors including the eleventh transistor. The same circuit structure serves both normal display operation and comprehensive transistor testing, eliminating the need for separate test hardware and reducing overall device complexity while improving reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If the eleventh transistor is always active to improve test coverage, then the defect detectability is improved, but the power consumption increases

Engineering Contradiction:
Improvetransistor defect detectabilityVSAvoidpixel power consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The eleventh transistor is activated periodically during initialization periods rather than continuously. The test mode is enabled at specific intervals (e.g., during vertical blanking periods or frame initialization) to verify transistor functionality, then deactivated during normal operation to minimize power consumption while maintaining reliability through regular testing.

Inventive Principle:
Principle #19Periodic action

3Reliability

If a test mode is implemented to detect defects, then the reliability is improved, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvedefect detection capabilityVSAvoidtransistor connection precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The test functionality is merged with the existing pixel circuit structure by utilizing the same transistor gates and nodes for both normal operation and testing. The eleventh transistor is integrated into the existing circuit topology, sharing connections with other components, which reduces the need for additional precise manufacturing steps while enabling comprehensive defect detection.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12505794B2Pixel and display device
Publication Date: 2025.12.23 SAMSUNG DISPLAY CO LTD
  • US12505794B2 patent drawing
  • US12505794B2 patent drawing
  • US12505794B2 patent drawing

AI summary

A pixel includes a first capacitor electrically connected between a first node and a second node, a second capacitor electrically connected between a first driving voltage line providing a first driving voltage and the first node, a light emitting diode including a first electrode and a second electrode electrically connected with a second driving voltage line providing a second driving voltage, first to fourth transistors, each including a first electrode, a second electrode, and a gate.