Pixel Circuit Threshold Compensation for High-Refresh Displays
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Solution Overview
Problem
Display devices face challenges in accurately compensating for data voltage due to varying threshold voltages of driving transistors, especially at higher resolutions and frequencies, leading to inconsistent luminance and potential image quality issues.
Innovation Solution
A display device design that includes specific transistor configurations and gate driver signals to accurately compensate for threshold voltages, separating compensation and data writing operations and using dual gate transistors to reduce leakage currents and voltage fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the resolution and driving frequency of the display device are increased, then the display quality and refresh rate are improved, but the data writing period becomes narrow making it difficult to appropriately compensate for data voltage
Solution Approach 1:
The pixel circuit is divided into multiple functional blocks with separate transistors for data writing (second transistor), compensation (third transistor), and emission control (fifth transistor). This segmentation allows independent optimization of each function, enabling sufficient compensation time even at high driving frequencies by separating the compensation operation from the data writing operation.
Solution Approach 2:
The compensation operation is performed in advance during a dedicated compensation period before the data writing period. The third transistor is turned on to compensate for the threshold voltage of the first transistor, and the compensation voltage is stored in the first capacitor before data writing begins, ensuring compensation is complete before data writing starts.
2Device complexity
If a simple pixel structure is used, then the device complexity is reduced, but the ability to sufficiently compensate for data voltage at high driving frequencies is compromised
Solution Approach 1:
The pixel circuit uses multiple transistors (first, second, third, fifth, sixth transistors) and capacitors (first, second capacitors) that are segmented into distinct functional blocks. Each transistor has a specific role: the first transistor controls the light emitting element, the second transistor writes data, the third transistor performs compensation, and the fifth transistor controls emission. This segmentation ensures reliable compensation while maintaining a manageable structure.
Solution Approach 2:
The first capacitor serves multiple functions: it stores the compensation voltage for the first transistor and also maintains the gate voltage during the emission period. The gate electrode of the first transistor is electrically connected to the first node, which is connected to the first capacitor, allowing the capacitor to perform both compensation storage and voltage maintenance functions.
3Manufacturing precision
If the data writing period is extended to allow proper compensation, then the data voltage compensation accuracy is improved, but the driving frequency must be reduced
Solution Approach 1:
The display operation is divided into distinct periods: a compensation period for voltage compensation, a data writing period for data input, and an emission period for light output. By segmenting these operations in time, the patent achieves sufficient compensation accuracy without extending the overall frame period, thereby maintaining high driving frequencies.
Solution Approach 2:
The pixel circuit operates in periodic cycles with distinct phases: compensation phase (third transistor on), data writing phase (second transistor on), and emission phase (fifth transistor on). This periodic action allows each function to be performed with sufficient time allocation while maintaining high overall driving frequency through efficient phase transition.
Data Source
AI summary
A display device is disclosed that includes a pixel. The pixel includes a first transistor connected between a second node and a third node and including a gate electrode connected to a first node. A first capacitor is formed between the first node and a fourth node. A second capacitor is formed between the fourth node and a first power line. A second transistor is connected between a data line and the fourth node. An eighth transistor is connected between the first power line and the second node. A ninth transistor is connected between the second node and a bias power line. A sixth transistor is connected between the third node and a fifth node. A light emitting element is electrically connected between the fifth node and a second power line. A gate electrode of the eighth transistor and a gate electrode of the sixth transistor are connected to different gate lines.