Pixel Circuit Timing for Display Hysteresis Compensation

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Solution Overview

Problem

Display devices experience momentary residual images due to hysteresis in driving transistors, particularly when transitioning from low to high luminance levels.

Innovation Solution

The pixel design incorporates multiple transistors and a specific timing scheme for scan signals to minimize hysteresis effects, including a second transistor turned on during a partial period of the third transistor's turn-on period, and a bias transistor with a voltage higher than initialization power, along with a unique scan driver configuration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional pixel design with a single driving transistor is used, then the device structure is simple, but momentary residual images occur due to hysteresis when transitioning from low to high luminance

Engineering Contradiction:
Improvedisplay qualityVSAvoidtransistor configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The pixel circuit is divided into multiple functional transistor units: a driving transistor for current control, a second transistor for data signal input, a third transistor for initialization, and a bias transistor for hysteresis compensation. This segmentation allows each transistor to perform a specific function, enabling effective prevention of momentary residual images while maintaining manageable circuit complexity through modular functional design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The third transistor applies an initialization power voltage to the gate of the driving transistor before the data signal is input, pre-setting the driving transistor in a specific state. This preliminary action ensures that the driving transistor starts from a known state, preventing hysteresis-induced momentary residual images when transitioning from low to high luminance displays.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 3:

The bias transistor dynamically adjusts the voltage parameter at the gate of the driving transistor based on the scan signal timing. By changing the voltage parameter through the bias transistor's controlled operation, the system compensates for hysteresis effects and maintains stable driving conditions, effectively preventing momentary residual images.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the second transistor is turned on during the third transistor's turn-on period, then initialization effectiveness is improved, but power consumption increases

Engineering Contradiction:
Improveinitialization effectivenessVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The second and third transistors are operated in a periodic manner during the non-emission period, with their turn-on periods overlapping to ensure effective initialization. This periodic operation is synchronized with the display frame timing, allowing the transistors to remain off during emission to conserve power while being active only when needed for initialization, thus balancing initialization effectiveness with power consumption.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20260080832A1Pixel and display device including the same
Publication Date: 2026.03.19 SAMSUNG DISPLAY CO LTD
  • US20260080832A1 patent drawing
  • US20260080832A1 patent drawing
  • US20260080832A1 patent drawing

AI summary

A pixel includes: a first transistor including a gate electrode connected to a first node, a first electrode connected to a first power line for receiving a first driving power voltage via a second node, and a second electrode connected to a third node; a light-emitting element including a first electrode connected to the third node, and a second electrode connected to a second power line; a second transistor connected between a data line and the second node, and including a gate electrode connected to a first scan line; and a third transistor connected between the first node and a third power line for receiving an initialization power voltage. The second transistor is set to a turn-on state during at least a portion of a turn-on period of the third transistor. The initialization power voltage is set to be lower than a data signal.