Pixel Transistor Inspection with Segmented Gate-Voltage Sampling
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Solution Overview
Problem
The increasing complexity of display devices leads to higher noise levels during direct current tests, prolonging inspection times and limiting the ability to detect defects in transistors effectively.
Innovation Solution
A method of inspecting pixels by varying the interval between gate voltages applied to a test transistor based on the period of gate voltage application, using multiple voltage intervals to generate drain current graphs and determine transistor defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a DC test is performed to measure electrical characteristics of the transistor, then the transistor defect can be detected, but noise increases and inspection time is prolonged
Solution Approach 1:
The patent applies periodic action by measuring drain current at multiple discrete gate voltage intervals rather than continuously. The gate voltage is varied in specific steps (e.g., 0V, 1V, 2V, 3V, 4V, 5V) and current measurements are taken at each interval. This periodic sampling approach reduces noise accumulation and filtering time while maintaining sufficient data points for accurate defect detection through characteristic curve analysis.
2Measurement precision
If gate voltage is applied continuously to measure drain current, then measurement data is obtained, but noise increases due to complex display structure
Solution Approach 1:
The patent segments the gate voltage range into discrete intervals and measures drain current at each specific interval. Instead of continuous measurement, the gate voltage is divided into segments (0V, 1V, 2V, 3V, 4V, 5V) and current is measured at each segment point. This segmentation isolates measurement points from continuous noise sources and enables clearer identification of transistor characteristics and defects.
Data Source
AI summary
A method of inspecting a pixel includes measuring a first drain current by applying a first gate voltage with a first voltage interval to a gate terminal of a transistor included in a test pattern in a first voltage period, generating a first gate voltage-drain current graph based on the first drain current, measuring a second drain current by applying a second gate voltage which is lower than the first gate voltage with a second voltage interval which is different from the first voltage interval to the gate terminal of the transistor in a second voltage period which is different from the first voltage period, generating a second gate voltage-drain current graph based on the second drain current, and determining a defect of the transistor based on the first gate voltage-drain current graph and the second gate voltage-drain current graph.