Pixel Transistor Layout for High-Speed High-Definition Displays
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Solution Overview
Problem
High-definition display apparatuses require high-speed operation and integration of transistors with minute sizes to enhance realism and immersion in virtual and augmented reality applications, while maintaining favorable electrical characteristics.
Innovation Solution
The display apparatus incorporates a pixel structure with specific transistor configurations, including multiple conductive layers and semiconductor layers, optimized by interlayer insulating layers to reduce parasitic capacitance and enable high-speed operation, and uses metal oxides like indium-zinc for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are made with minute sizes to increase integration, then the degree of integration is improved, but manufacturing precision becomes more difficult to control
Solution Approach 1:
The transistor structure is divided into multiple components (source region, channel region, drain region, gate electrode) that are formed through separate processes. The channel region is defined by spaces between source and drain regions, allowing independent control of each segment's dimensions and properties, thereby maintaining manufacturing precision while achieving high integration.
Solution Approach 2:
Different regions of the transistor are given different properties: the channel region has specific semiconductor characteristics while source and drain regions have different doping concentrations. The gate electrode is positioned to locally control the channel region's electrical properties, enabling precise control of transistor characteristics despite miniaturization.
2Productivity
If transistors are made with minute sizes to increase integration, then the degree of integration is improved, but device complexity increases
Solution Approach 1:
The gate electrode serves multiple functions: it controls the channel region's conductivity, defines the channel geometry, and can be configured in different shapes (linear, U-shaped, inverted U-shaped) to provide various control characteristics. This multi-functionality reduces the need for additional separate structures, thereby managing device complexity while maintaining high integration.
Solution Approach 2:
The gate electrode is positioned within or adjacent to the channel region, with the channel region nested between source and drain regions. The gate insulating layer is formed between the gate electrode and the channel region, creating a nested structure that efficiently uses space and reduces overall device complexity despite miniaturization.
3Speed
If display apparatus operates at high speed to ensure frame frequency, then display performance is improved, but parasitic capacitance increases
Solution Approach 1:
The gate insulating layer is extracted as a separate component formed between the gate electrode and the channel region. This separate insulating layer allows precise control of the electric field distribution, reducing parasitic capacitance between conductive regions while enabling high-speed operation through effective gate control.
Solution Approach 2:
The gate insulating layer acts as an intermediary between the gate electrode and the channel region, preventing direct electrical contact while allowing electric field coupling. This intermediary layer reduces parasitic capacitance by controlling the dielectric properties between conductive elements, enabling high-speed operation without excessive capacitance.
Data Source
AI summary
A display apparatus which is driven at high speed is provided. The display apparatus includes a pixel, a scan line driver circuit, and a power supply circuit. The pixel includes first and second transistors. In the second transistor, a semiconductor layer is provided in an opening formed in an interlayer insulating layer over a substrate. A first conductive layer functioning a gate electrode of the first transistor includes a region extending in the first direction and is electrically connected to the scan line driver circuit. A second conductive layer functioning as a source electrode or a drain electrode of the second transistor is provided below the opening. The second conductive layer includes a region extending in the second direction perpendicular to the first direction and is electrically connected to the power supply circuit. The first conductive layer and the second conductive layer include a region where they overlap with each other with the interlayer insulating layer therebetween.