Pixel Transistor Layout for Uniform Sensitivity in Image Sensors

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Solid-state imaging devices experience sensitivity differences between pixels due to variations in pixel arrangement and element isolation insulation film shapes, leading to inconsistent performance.

Innovation Solution

The implementation of a configuration where transistors in solid-state imaging devices are disposed periodically or symmetrically in specific directions, and the use of element isolation insulation films to prevent sensitivity differences and color mixing between pixels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If transistors are arranged in pixels with element isolation insulation films, then pixel isolation and color mixing prevention are achieved, but sensitivity differences between pixels occur due to arrangement variations and film shape variations

Engineering Contradiction:
Improvecolor mixing between pixelsVSAvoidsensitivity uniformity between pixels
Core Design Contradiction:
Object-affected harmful factorsVSMeasurement precision

Solution Approach 1:

The patent applies asymmetry by intentionally introducing dummy transistors with different configurations (different gate lengths, widths, or positions) to compensate for the asymmetric effects caused by element isolation insulation films. This creates a balanced overall structure where the asymmetric dummy transistors offset the asymmetric sensitivity variations, achieving uniform pixel sensitivity while maintaining effective isolation.

Inventive Principle:
Principle #4Asymmetry

2Object-affected harmful factors

If element isolation insulation films are used to surround pixels, then color mixing is prevented, but sensitivity differences are generated due to variations in film shape and pixel arrangement

Engineering Contradiction:
Improvecolor mixing between pixelsVSAvoidsensitivity consistency
Core Design Contradiction:
Object-affected harmful factorsVSManufacturing precision

Solution Approach 1:

The patent applies local quality by configuring dummy transistors with specific local characteristics (different gate dimensions, positions, or types) in specific pixel locations where sensitivity variations occur. This localized adjustment allows each pixel to be optimized individually to compensate for local variations in element isolation insulation film shapes and arrangements, achieving uniform sensitivity across the entire pixel array.

Inventive Principle:
Principle #3Local quality

3Productivity

If pixels are arranged in a two-dimensional array with transistors, then imaging functionality is achieved, but sensitivity differences occur due to arrangement and insulation film shape variations

Engineering Contradiction:
Improvepixel array imaging capabilityVSAvoidsensitivity uniformity
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent applies merging by integrating dummy transistors into the pixel structure alongside functional transistors. These dummy transistors are combined with the element isolation insulation films and pixel electrodes to form a unified pixel structure that simultaneously achieves color mixing prevention and sensitivity uniformity, maintaining full imaging functionality while compensating for sensitivity variations.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20230395617A1Solid-state imaging device
Publication Date: 2023.12.07 SONY SEMICON SOLUTIONS CORP
  • US20230395617A1 patent drawing
  • US20230395617A1 patent drawing
  • US20230395617A1 patent drawing

AI summary

There is provided a solid-state imaging device capable of preventing the sensitivity difference from being generated between the pixels.The fixed imaging device of the present disclosure includes: a first pixel; and a second pixel located in a first direction of the first pixel, in which each of the first and second pixels includes a first transistor and a second transistor, and the first and second transistors in the second pixel are disposed periodically in the first direction with respect to the first and second transistors in the first pixel.