Pixel Via Layer Profile to Prevent Alignment Electrode Cutting
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Solution Overview
Problem
Existing display devices face reliability issues due to the cutting of conductive patterns or alignment electrodes during the manufacturing process of via holes, leading to potential electrical disconnections and reduced performance.
Innovation Solution
A via layer with a smooth profile is designed near via holes, ensuring that conductive patterns and alignment electrodes within the holes are not cut, thereby maintaining electrical connections and improving the overall reliability of the pixel and display device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a via layer with conventional profile is used, then the manufacturing process is simple, but conductive patterns and alignment electrodes are cut during via hole formation, causing electrical disconnections
Solution Approach 1:
The via layer is designed with different thicknesses in different regions: a first thickness in the emission area and a second thickness (greater than the first) in the non-emission area surrounding via holes. This local quality variation ensures that conductive patterns and alignment electrodes are not cut during via hole formation while maintaining manufacturing feasibility.
Solution Approach 2:
The via layer profile is prepared in advance with a smooth transition region before via hole formation. The non-emission area is designed with increased thickness to preemptively prevent cutting of conductive patterns and alignment electrodes during the subsequent via hole etching process.
2Reliability
If the via layer thickness is increased uniformly, then conductive patterns are protected from cutting, but manufacturing complexity and material usage increase
Solution Approach 1:
Instead of uniform thickness increase, the via layer employs local quality variation with different thicknesses in specific regions. The non-emission area has increased thickness only where needed to protect conductive patterns, while the emission area maintains original thickness, optimizing both protection and manufacturability.
Solution Approach 2:
The via layer thickness parameter is changed locally rather than globally. The thickness varies from a first value in the emission area to a second value (greater than the first) in the non-emission area, allowing protection of conductive patterns without excessive material usage or manufacturing complexity.
3Productivity
If via holes are formed with conventional methods, then manufacturing is efficient, but alignment electrodes and conductive patterns are damaged
Solution Approach 1:
The via layer structure incorporates local quality variation with increased thickness in the non-emission area surrounding via holes. This localized structural modification protects conductive patterns and alignment electrodes during conventional via hole formation processes without requiring changes to the manufacturing method itself.
Solution Approach 2:
The via layer is designed with a cushioning effect in the non-emission area where the increased thickness acts as a buffer zone. This beforehand cushioning prevents the cutting of conductive patterns and alignment electrodes during via hole etching, maintaining manufacturing precision while preserving productivity.
Data Source
AI summary
A pixel includes: a first conductive pattern, a second conductive pattern, and a third conductive pattern on a substrate and spaced apart from each other; a passivation layer on and exposing each of the first, second, and third conductive patterns; a via layer on the passivation layer and having first, second, and third via holes respectively exposing one area of the first conductive pattern, one area of the second conductive pattern, and one area of the third conductive pattern; first and second alignment electrodes on the via layer and electrically connected to the second conductive pattern and the first conductive pattern, respectively; and a light emitting element on the first and second alignment electrodes. The via layer has a first area and a second area that is thinner than the first area, and the second area is directly adjacent to at least one of the via holes.