Pixel Voltage Line Layout Across Metal Layers for High-Resolution Displays
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Solution Overview
Problem
Existing display devices face challenges in manufacturing processes due to high pattern density of metal lines, which can lead to contact defects between different metal layers and limited design margins.
Innovation Solution
The display device design disperses metal lines across different metal layers, with some data lines positioned at the gate layer, eliminating the need for connection electrodes and preventing short-circuit defects, while integrating gate lines and auxiliary gate lines at the same layer to avoid contact defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If metal lines are densely arranged in existing display devices, then high-resolution display is achieved, but contact defects between different metal layers occur and design margins are limited
Solution Approach 1:
The patent applies dimensionality change by moving data lines from the first metal layer to the gate layer, which is a different layer dimension. This spatial redistribution across multiple layers reduces the pattern density on any single layer, thereby preventing contact defects while maintaining high-resolution display capabilities.
2Measurement precision
If metal lines are densely arranged in existing display devices, then high-resolution display is achieved, but manufacturing process difficulty increases
Solution Approach 1:
By utilizing the gate layer as an additional dimensional space for routing data lines, the patent reduces the pattern density on the first metal layer. This makes the manufacturing process easier by reducing the complexity of photolithography and etching steps required for high-resolution displays.
3Reliability
If connection electrodes are used to connect data lines to pixel circuits, then electrical connection is achieved, but device complexity and contact defect risk increase
Solution Approach 1:
The patent merges the data line function with the gate layer structure. By forming data lines directly on the gate layer that overlap with pixel circuits, the patent eliminates the need for separate connection electrodes, thereby reducing device complexity and contact defect risk while maintaining reliable electrical connection.
4Reliability
If metal lines are dispersed across different layers, then contact defects are prevented and design margins are secured, but manufacturing steps increase
Solution Approach 1:
The patent segments the metal line routing into different layers: data lines are routed on the gate layer while other metal lines remain on the first metal layer. This segmentation prevents contact defects by separating potentially interfering lines, and the process integrates well with existing multi-layer fabrication techniques to maintain manufacturing efficiency.
Data Source
AI summary
A display device includes a first pixel, a second pixel, and a third pixel, each disposed on a substrate and including a pixel circuit, a first metal line disposed at a first metal layer on the substrate, extending in a first direction on a first side of the pixel circuits of the first to third pixels, and electrically connected to at least one of the pixel circuits of the first to third pixels, a second metal line disposed at a second metal layer on the first metal layer, extending in the first direction on a first side of the first metal line, and electrically connected to at least one of the pixel circuits of the first to third pixels, and a third metal line disposed at the first metal layer, extending in the first direction on a first side of the second metal line, and electrically connected to at least one of the pixel circuits of the first to third pixels. Each of the first to third metal lines supplies a voltage to at least one of the pixel circuits of the first to third pixels.