Pixel Voltage Time Division for Latency and Power Reduction
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Solution Overview
Problem
Display devices with high resolution face challenges in reducing latency without increasing the number of transistors in pixels, particularly when handling external inputs during variable driving frequencies.
Innovation Solution
The pixel design includes a light emitting element connected through a series of transistors and a storage capacitor, with voltage time division from data voltage to on-bias voltage in a time unit, allowing for efficient operation during both display scan and self-scan periods, and utilizing specific scan signals and emission control signals to manage transistor states and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the number of transistors in a pixel is increased to reduce latency, then latency decreases, but device complexity increases
Solution Approach 1:
The patent implements dynamic scanning where scan lines are selectively activated based on whether a touch input is detected. During self-scan periods, only necessary scan lines are activated, and the scanning frequency is dynamically adjusted. This allows the system to reduce latency for touch inputs without permanently increasing the number of active transistors, as the complexity is managed through time-varying configuration rather than static hardware expansion.
Solution Approach 2:
The patent employs periodic self-scan periods interspersed with display scan periods. During self-scan periods, the system periodically checks for touch inputs and updates corresponding scan lines. This periodic action allows the system to maintain low latency for touch events while keeping the overall transistor activation pattern manageable through rhythmic, predictable cycles rather than continuous high-complexity operation.
2Loss of time
If the scanning frequency is increased to improve responsiveness, then latency decreases, but power consumption increases
Solution Approach 1:
The scanning frequency is dynamically adjusted based on operational mode. During display scan periods, the system operates at normal refresh rates. When touch input is detected during self-scan periods, the system transitions to higher frequency scanning for the affected scan lines to reduce latency. This dynamic frequency adjustment ensures fast response when needed while maintaining lower power consumption during normal operation.
Solution Approach 2:
The system uses periodic self-scan periods at lower frequency to detect touch inputs, then activates higher frequency scanning only for the specific scan lines where touch events occur. This selective periodic high-frequency operation reduces overall power consumption compared to continuously running all scan lines at high frequency, while still achieving low latency for touch events.
3Adaptability or versatility
If the display operates at variable driving frequency, then adaptability improves, but image quality stability deteriorates
Solution Approach 1:
The patent segments the scanning operation into distinct display scan periods and self-scan periods. Display scan periods maintain stable, consistent timing for image rendering, while self-scan periods handle touch input detection with flexible timing. This segmentation allows variable frequency operation during self-scan without compromising the stability of image quality during display scan periods, as the two functions are temporally separated.
Solution Approach 2:
The system dynamically switches between different scanning modes while maintaining stable image quality through careful timing management. During display scan periods, the timing is stabilized for consistent image rendering. During self-scan periods, the timing is flexible to detect touch inputs. This dynamic mode switching with stabilized timing during critical display operations allows variable frequency operation without degrading image quality.
Data Source
AI summary
A pixel includes a light emitting element, a first transistor connected to the light emitting element, a second transistor connected between a data line and a first electrode of the first transistor, a third transistor connected between a gate electrode of the first transistor T1 and a second electrode of the first transistor, a fourth transistor connected between a gate electrode of the first transistor and an initialization power source, and a storage capacitor connected between the first power source and the gate electrode of the first transistor. A voltage provided through the data line is time divided into a data voltage provided to the gate electrode of the first transistor when both the second and third transistors turn on, and an on-bias voltage provided to the first electrode of the first transistor when the second transistor turns on and the third transistor turns off.