Pixel Wait Synchronization for Graphics Pipeline Efficiency

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Solution Overview

Problem

In graphics processing systems, back-to-back dependent draw calls result in a full graphics pipeline drain due to the need to flush and invalidate caches, leading to inefficiencies in rendering processes.

Innovation Solution

Implementing a pixel wait synchronization mechanism where a wait sync event is issued by the command processor to the graphics pipeline, allowing dependent draw calls to proceed only when the previous draw call has completed by using an event counter to track in-flight draw calls and ensuring that dependencies are resolved before processing continues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the graphics pipeline flushes and invalidates the first cache after completing a draw to the writeable surface, then the data consistency is ensured, but the pipeline drain time increases

Engineering Contradiction:
Improvedata consistencyVSAvoidpipeline drain time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary cache validation by attaching a validation bit to the writeable surface before the dependent draw call executes. This allows the pipeline to proceed without waiting for the full flush to complete, as the validation bit is set in advance during the first draw call's completion notification.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The validation bit acts as an intermediary mechanism between the cache flush operation and the dependent draw call. Instead of requiring the full flush to complete before proceeding, the validation bit serves as a lightweight indicator that sufficient validation has occurred, allowing the pipeline to drain faster while maintaining data consistency.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the graphics pipeline waits for the flush to commit to the second cache or memory, then the data availability is ensured, but the rendering efficiency decreases

Engineering Contradiction:
Improvedata availabilityVSAvoidrendering efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system sets the validation bit as a preliminary action during the first draw call's completion notification, before the dependent draw call needs to access the data. This allows the dependent draw call to proceed without waiting for the flush to fully commit, improving rendering efficiency while maintaining data availability through the validation mechanism.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The validation bit mechanism allows the graphics pipeline to self-validate data availability without requiring external intervention or full flush completion. The pipeline can autonomously determine when data is ready based on the validation bit state, improving efficiency while ensuring data availability.

Inventive Principle:
Principle #25Self-service

3Reliability

If the graphics pipeline attaches the surface to the second cache after flush, then the cache management is correct, but the pipeline stall time increases

Engineering Contradiction:
Improvecache management correctnessVSAvoidpipeline stall time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs the surface attachment operation as a preliminary action during the first draw call's completion notification, before the dependent draw call needs to access the surface. This allows the pipeline to avoid stalls by having the attachment already in place, while maintaining cache management correctness through the validation bit mechanism.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10796399B2Pixel wait synchronization
Publication Date: 2020.10.06 ADVANCED MICRO DEVICES INC
  • US10796399B2 patent drawing
  • US10796399B2 patent drawing
  • US10796399B2 patent drawing

AI summary

Systems, apparatuses, and methods for implementing pixel wait synchronization techniques are disclosed. A system includes a host processor and a graphics processor which includes at least one graphics pipeline. During execution of a graphics application, the host processor determines that a second draw call is dependent on a first draw call. The host processor issues a wait sync event prior to issuing the second draw call to the graphics pipeline responsive to determining that the first draw call is still in-flight in the graphics pipeline. After the second draw call is issued to the graphics pipeline, the second draw call is processed by one or more stages of the graphics pipeline while the first draw call is still in-flight. The graphics pipeline stalls the second draw call at a given intermediate stage until a corresponding event counter equals a value specified by the wait sync event.