Multilayer Pixel Wiring in Array Substrates for Smaller Pixels
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Solution Overview
Problem
Existing display devices with pixel circuits containing multiple transistors and capacitances face challenges in efficiently disposing wiring due to the large number of elements and wires, leading to potential difficulties in optimizing the layout and reducing the area of each pixel.
Innovation Solution
The display device employs a substrate with multiple pixels, light emitting elements, and transistors, utilizing a layered metal structure with different insulating films to efficiently arrange signal lines and power supply lines, allowing for reduced pixel area and improved resolution by separating wiring layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple transistors and capacitances are used in each pixel circuit, then the display device achieves improved functionality and performance, but the wiring becomes more complex and difficult to dispose efficiently
Solution Approach 1:
The patent transitions from planar wiring layout to three-dimensional stacked architecture by placing transistors, capacitances, and wiring in multiple vertical layers. This dimensional change allows complex pixel circuits to be organized in the vertical direction rather than spreading out horizontally, reducing wiring complexity while maintaining full functionality.
Solution Approach 2:
The pixel circuit is segmented into distinct functional blocks distributed across multiple layers: light emitting elements in one layer, transistors in another, capacitances in a third, and wiring layers interleaved between them. This segmentation allows each component type to be optimized independently and simplifies the overall wiring architecture.
2Reliability
If more elements and wires are packed into each pixel, then the display device achieves higher functionality, but the pixel area increases and resolution is reduced
Solution Approach 1:
By stacking pixel circuit elements vertically across multiple layers, the patent confines the horizontal footprint of each pixel while accommodating all necessary functional elements. The vertical stacking allows high-density integration without increasing pixel area, thereby maintaining or improving resolution.
Solution Approach 2:
The patent implements a nested layer structure where different functional components are embedded within each other vertically: wiring layers are positioned between transistor layers, capacitances are integrated alongside transistors, and light emitting elements are coupled to the transistor array. This nesting maximizes space utilization within each pixel area.
3Ease of manufacture
If wiring is arranged in a single layer, then the manufacturing process is simpler, but the efficiency of wiring disposition is reduced
Solution Approach 1:
The patent extends the wiring architecture from a single layer to multiple stacked layers, with each layer dedicated to specific wiring functions. This multi-layer approach improves wiring disposition efficiency by allowing signals to route vertically between layers through via holes, reducing the need for long horizontal traces and improving signal integrity.
Solution Approach 2:
The patent combines multiple wiring layers into an integrated three-dimensional network that works together as a unified system. Signal lines, power lines, and ground lines are distributed across different layers and interconnected through vertical vias, creating an efficient wiring architecture that balances manufacturing feasibility with high wiring density.
Data Source
AI summary
A display device includes a substrate, a plurality of pixels provided to the substrate, a light emitting element and a plurality of transistors provided to each of the pixels, a plurality of signal lines configured to supply a signal to the pixels, a power supply line configured to supply a drive potential to the pixels, a first metal layer, a second metal layer, and a third metal layer provided in different layers in a direction perpendicular to the substrate, a first insulating film provided between the first metal layer and the second metal layer, and a second insulating film provided between the second metal layer and the third metal layer.