Pixel Driving Circuit Wiring Layout for OLED Crosstalk Reduction
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Solution Overview
Problem
In OLED displays, parasitic capacitances between data signal lines and the gate and source of driving transistors cause uneven local brightness due to differing voltage jumps, leading to crosstalk issues.
Innovation Solution
The wire layout of the pixel driving circuit is redesigned to increase the distance between the data signal line and the gate of the driving transistor, reduce coupling by avoiding overlap with the scan signal line, and enhance coupling with the power signal line, using MOS transistors and storage capacitors to stabilize the voltage difference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data signal line is positioned closer to the gate of the driving transistor, then the coupling between the data signal line and the gate is stronger, but the voltage jump difference between gate and source increases causing brightness unevenness and crosstalk
Solution Approach 1:
The patent introduces a multi-layer wiring structure where signal lines are arranged on different layers (first layer and second layer) rather than only in the same plane. The data signal line on the first layer and power signal line on the second layer are positioned to reduce parasitic capacitance coupling, while still maintaining functional connectivity through vertical vias. This dimensional arrangement resolves the contradiction by spatially separating interfering signals while preserving necessary electrical connections.
Solution Approach 2:
The patent introduces compensation capacitors as intermediary elements that are coupled to the gate and source of the driving transistor. These capacitors serve as mediators to compensate for the voltage jump differences caused by parasitic capacitances between signal lines and transistor terminals. By adding this intermediary compensation mechanism, the system can tolerate closer signal line positioning while maintaining brightness uniformity.
2Area of stationary object
If the data signal line and scan signal line overlap, then the area utilization is improved, but the parasitic capacitance coupling increases causing voltage interference
Solution Approach 1:
The patent positions the data signal line and scan signal line on different vertical layers rather than allowing them to overlap in the same plane. The data signal line resides on the first layer while the scan signal line is on the second layer, eliminating direct parasitic capacitance coupling between these two critical signal lines. This layered dimensional arrangement maintains compact pixel area while removing harmful electromagnetic interference.
Solution Approach 2:
The patent extracts the harmful overlapping region between data and scan signal lines by separating them into different layers. The overlapping spatial region that would create parasitic capacitance is eliminated by vertically separating the signal lines, while the pixel circuit still achieves compact area utilization through the three-dimensional layering of other circuit elements.
3Object-affected harmful factors
If the power signal line is positioned farther from the gate of the driving transistor, then the coupling with the gate is reduced, but the voltage jump difference between gate and source increases
Solution Approach 1:
The patent introduces compensation capacitors connected between the gate and source terminals of the driving transistor as intermediary elements. These capacitors actively compensate for voltage jump differences that occur when the power signal line is positioned farther from the gate. The compensation capacitor serves as a mediator that maintains voltage difference stability regardless of the physical distance between the power signal line and gate, resolving the contradiction between reducing interference and maintaining voltage stability.
Data Source
AI summary
Provided are a wiring structure of a pixel driving circuit, a display panel, and a display device. The wire layout includes: a first switching element, a second switching element and a driving transistor. A source electrode of the driving transistor is connected to a power signal line. The power signal line includes a first power signal line that is in a same direction as a data signal line, and the data signal line is arranged at a position of the first power signal line away from a gate electrode of the driving transistor.