Display Pixel Wiring Shielding for Parasitic Capacitance Control
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Solution Overview
Problem
As display devices are miniaturized for higher resolution, parasitic capacitance and off-current issues arise due to reduced intervals between thin film transistors (TFTs) and wirings, affecting image quality and emission control.
Innovation Solution
A display device design that includes a shielding portion between the data line and node connection line, featuring a semiconductor and metallic shielding layer, connected to the initialization voltage line, to reduce parasitic capacitance and off-current, and incorporates a compensation TFT that diode-connects the driving TFT to improve image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If intervals between TFTs and wirings are reduced to implement miniaturized or high resolution display device, then display resolution and miniaturization are improved, but parasitic capacitance increases
Solution Approach 1:
A shielding portion is introduced as an intermediary element positioned between the data line and node connection line. This shielding portion includes a shielding semiconductor layer and a metallic shielding layer that act as mediators to block parasitic capacitance coupling between adjacent wirings, thereby resolving the harmful effect of reduced wiring intervals while maintaining high display resolution
Solution Approach 2:
The harmful parasitic capacitance effect is extracted and isolated by introducing a dedicated shielding structure. The shielding portion separates the problematic electromagnetic coupling from the functional wiring, allowing the main display circuitry to operate at high resolution without the detrimental effects of parasitic capacitance
2Manufacturing precision
If intervals between TFTs and wirings are reduced to implement miniaturized or high resolution display device, then display resolution and miniaturization are improved, but off-current increases
Solution Approach 1:
The shielding portion acts as an intermediary barrier that prevents unwanted electrical interactions between adjacent wirings. By positioning the shielding semiconductor layer and metallic shielding layer between the data line and node connection line, off-current generated due to reduced intervals is blocked, thereby maintaining high display resolution while reducing harmful off-current
Solution Approach 2:
The shielding structure converts the potentially harmful close proximity of wirings into a beneficial arrangement. By deliberately positioning shielding layers at these critical interfaces, the design transforms the problematic reduced intervals into an opportunity for targeted parasitic capacitance and off-current management, allowing high resolution display without suffering from the usual penalties of wiring crowding
Data Source
AI summary
A display device includes a scan line extending in a first direction, a data line and a driving voltage line extending in a second direction crossing the first direction, a switching thin film transistor (“TFT”) connected to the scan line and the data line, a driving TFT connected to the switching TFT and including a driving semiconductor layer and a driving gate electrode, a storage capacitor connected to the driving TFT and including first and second storage capacitor plates, a node connection line between the data line and the driving voltage line and connected to the driving gate electrode, and a shielding portion between the data line and the node connection line.