PL Master Address Translation via Dedicated SMMU Interface

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Solution Overview

Problem

Programmable logic masters in system-on-chip (SoC) designs face challenges with virtual-to-physical address translation, particularly for circuits with internal caches, as they cannot route their traffic through the processing system's memory management unit (PS SMMU), leading to latency and inefficiencies.

Innovation Solution

A hardware-based virtual-to-physical address translation solution is implemented using a system memory management unit (SMMU) with an additional port for address translation requests, eliminating clock domain crossing latency and allowing PL masters to operate independently of the PS SMMU for traffic other than translation requests.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If PL masters route traffic through the PS SMMU for address translation, then virtual-to-physical address translation is provided, but traffic latency increases and PS resources are consumed

Engineering Contradiction:

Improveaddress translation capabilityVSAvoidtraffic latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the address translation function from the main PS SMMU path by providing a dedicated SMMU instance for PL masters. This separate translation path allows PL traffic to be translated independently without contending for PS SMMU resources, thereby reducing latency while maintaining translation capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary connection between PL masters and the SMMU that enables direct address translation requests. This intermediary path bypasses the PS routing requirement, allowing PL masters to access translation services directly without going through the PS SMMU traffic path.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If PL masters with internal caches route traffic through the PS, then the PS SMMU can be used for virtualization, but the internal caches cannot perform address translation prior to cache access

Engineering Contradiction:

Improvevirtualization capabilityVSAvoidcache access efficiency

Core Design Contradiction:

Adaptability or versatilityVSEase of operation

Solution Approach 1:

The patent provides a dedicated SMMU instance that can be independently configured for PL masters with internal caches. This segmentation allows these masters to perform address translation before cache access through their own translation path, enabling efficient cache operation while maintaining virtualization support through separate configuration.

Inventive Principle:

Principle #1Segmentation

3Productivity

If a dedicated SMMU instance is provided for PL masters, then address translation latency is reduced, but device complexity increases

Engineering Contradiction:

Improveaddress translation speedVSAvoidSMMU architecture complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent designs the dedicated SMMU instance for PL masters to share common infrastructure with the PS SMMU, including translation lookup structures and control logic. This multi-functionality approach allows the same translation engine to serve both PS and PL masters, reducing the actual complexity increase while maintaining dedicated translation paths.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11327899B1Hardware-based virtual-to-physical address translation for programmable logic masters in a system on chip

Publication Date: 2022.05.10 XILINX INC

AI summary

An example programmable integrated circuit (IC) includes a processing system having a processor, a master circuit, and a system memory management unit (SMMU). The SMMU includes a first translation buffer unit (TBU) coupled to the master circuit, an address translation (AT) circuit, an AT interface coupled to the AT circuit, and a second TBU coupled to the AT circuit, and programmable logic coupled to the AT circuit in the SMMU through the AT interface.