Programmable Logic Array Routing for Timing-Safe Flip-Flops
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Solution Overview
Problem
In integrated circuits with programmable logic arrays (PLAs), ensuring proper timing relationships between flip-flops is challenging due to unpredictable combinational path delays, leading to potential timing errors and frustration for programmers.
Innovation Solution
The PLA is designed with hardware-level constraints that only allow connection paths ensuring proper timing, featuring direct and synchronized outputs, where direct outputs are restricted from connecting to logic elements of lower rank to prevent timing errors, thus ensuring safe setup times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If direct output connections are allowed to any logic element, then programming flexibility is improved, but timing errors increase
Solution Approach 1:
The output connections are segmented into two distinct types: direct outputs and synchronized outputs. Direct outputs provide fast, unsynchronized connections to logic elements of higher rank, while synchronized outputs provide clock-synchronized connections to all logic elements. This segmentation allows the system to offer both fast direct routing and timing-safe synchronized routing, resolving the contradiction between flexibility and timing reliability.
Solution Approach 2:
Different connection paths are provided with different timing characteristics based on the destination. Direct outputs offer minimal delay to higher-rank elements, while synchronized outputs ensure proper setup/hold times for all destinations. The programming interface allows selection of the appropriate output type based on the specific routing need, providing locally optimized timing characteristics for each connection.
2Ease of operation
If all connection paths are permitted, then programming freedom is improved, but setup time violations increase
Solution Approach 1:
The PLA structure pre-establishes two types of output paths before programming: direct outputs that inherently satisfy timing to higher-rank elements, and synchronized outputs that are clock-aligned. This preliminary structuring of connection options ensures that regardless of how the user programs the logic, the physical connection paths are already designed to meet setup time requirements, eliminating the need for post-programming timing verification.
Solution Approach 2:
Synchronized outputs act as an intermediary mechanism between the logic elements and the clock domain. By introducing this intermediate synchronized path, the system mediates between the need for flexible direct connections and the requirement for timing compliance, allowing programmers to achieve any logic function while maintaining setup time guarantees through the synchronized path.
Data Source
AI summary
An integrated circuit includes a programmable logic array. The programmable logic array incudes a plurality of logic elements arranged in rows and columns. Each logic element includes a direct output and a synchronized output. The direct output of each logic element is coupled to all other logic elements of higher rank, but is not coupled to logic elements of lower rank.