PLA Input Signal Conditioning for Glitch-Free Clock Synchronization
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Solution Overview
Problem
Integrated circuits with programmable logic arrays (PLAs) face issues with input signals having unknown characteristics, leading to glitches and unpredictable behavior, which can result in faulty outputs due to asynchronous signals and unconditioned data processing.
Innovation Solution
The integrated circuit includes a signal conditioner with an edge detector, synchronizer, and filter, along with customizable multiplexers, allowing users to selectively condition input signals for the PLA, ensuring reliable processing by shaping and synchronizing the inputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If input signals are passed to the PLA without conditioning, then the circuit complexity is reduced, but the reliability of the PLA output deteriorates due to glitches and unpredictable behavior
Solution Approach 1:
A signal conditioner is introduced as an intermediary component between the input signals and the PLA. This signal conditioner includes an edge detector that generates shaped pulse signals from unconditioned inputs, and multiplexers that selectively route either conditioned or unconditioned signals to the PLA based on control logic, thereby improving reliability without forcing full conditioning on all signals
Solution Approach 2:
The signal conditioner incorporates multiplexers that dynamically select between conditioned and unconditioned signal paths based on runtime conditions. This dynamic switching capability allows the system to adaptively choose the appropriate signal processing path, balancing reliability needs against complexity constraints on a per-signal basis
2Reliability
If an edge detector is used to shape input signals, then the reliability of PLA processing is improved, but the device complexity increases due to additional conditioning components
Solution Approach 1:
The signal conditioner is segmented into modular functional blocks: an edge detector for signal shaping, multiple multiplexers for selective routing, and control logic for coordination. This segmentation allows each component to perform its specific function efficiently and enables independent optimization or removal of individual modules based on application requirements
Solution Approach 2:
The signal conditioner is designed with universal components that can handle multiple signal types and conditioning requirements. The multiplexers can route signals through different paths (conditioned or unconditioned), and the edge detector can process various input signal formats, making the conditioner applicable to diverse PLA input scenarios without requiring custom design for each case
3Adaptability or versatility
If signal conditioning is made customizable with multiplexers, then the adaptability to different signal types is improved, but the ease of operation deteriorates due to increased configuration requirements
Solution Approach 1:
The signal conditioner incorporates control logic that automatically manages the multiplexer selection and signal routing based on detected signal characteristics or pre-configured parameters. This self-service capability reduces the manual configuration burden on users while maintaining high adaptability to different signal types, as the system autonomously determines the appropriate conditioning path
Data Source
AI summary
A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.