PLA Input Signal Shaping With Edge Detection and Synchronization
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Solution Overview
Problem
Integrated circuits with programmable logic arrays (PLAs) face issues with input signal conditioning, leading to potential glitches and errors due to unknown signal characteristics, such as source clocks and routing parameters, which can result in unpredictable asynchronous signals.
Innovation Solution
The integration of a customizable signal conditioner within the integrated circuit, featuring an edge detector, synchronizer, and filter, along with multiplexers, allows for selective conditioning of input signals to ensure reliable processing by the PLA, enabling users to control the shaping of inputs through programmable options.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If input signals are passed to the PLA without conditioning, then the device complexity is reduced, but the reliability deteriorates due to glitches and unpredictable asynchronous signals
Solution Approach 1:
A signal conditioner is introduced as an intermediary component between the input signals and the PLA. This conditioner includes an edge detector that converts unknown input signal shapes into standardized pulse signals with known characteristics, and a synchronizer that aligns these pulses with the PLA clock signal. This intermediary structure ensures reliable signal processing while maintaining relatively simple circuit implementation.
2Stability of the object's composition
If an edge detector is used to convert input signals into pulse signals, then the signal shape predictability is improved, but the device complexity increases
Solution Approach 1:
The signal conditioning function is segmented into distinct modular components: an edge detector module that generates pulses from input signals, a synchronizer module that aligns pulses with the clock signal, and multiplexers that provide selective signal routing. This segmentation allows each component to perform its specific function with simple circuitry while collectively achieving stable and predictable signal shaping.
3Reliability
If a synchronizer is added to synchronize input signals with the PLA clock, then the reliability is improved, but the loss of time increases due to additional processing steps
Solution Approach 1:
The synchronizer is designed to perform synchronization in advance of the main PLA operation. By pre-aligning the edge-detected pulses with the PLA clock signal before the pulses enter the logic array, the system ensures that all subsequent logic operations receive properly synchronized inputs without requiring additional delay compensation throughout the circuit. This preliminary synchronization minimizes overall processing time while maintaining reliability.
4Adaptability or versatility
If multiplexers are used to provide selective signal routing, then the adaptability is improved, but the device complexity increases
Solution Approach 1:
The multiplexers in the signal conditioner are designed with multi-functionality to handle various signal routing scenarios. The same multiplexer structure can selectively pass either the original input signal or the edge-detected pulse signal to the PLA, depending on the desired operating mode. This universal design provides routing flexibility without requiring separate dedicated circuits for each function, thereby limiting the increase in overall device complexity.
Data Source
AI summary
A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.