Simultaneous Place-and-Route Using Random Normalized Polish Expressions
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Solution Overview
Problem
Current electronic design automation tools for integrated circuits face challenges in efficiently handling complex layouts and achieving optimal placement and routing, particularly for analog circuits, leading to issues with parasitics, circuit performance, and signal integrity.
Innovation Solution
The implementation of a simultaneous automatic placement and routing system using a shape-based approach within electronic design automation (EDA) software, which allows for compact layouts, reduced parasitics, and improved performance characteristics by employing a gridless system that efficiently handles off-grid connections and post-route optimizations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional grid-based placement and routing systems are used, then the layout process is simplified and standardized, but the layouts cannot achieve optimal compactness and increased parasitics occur due to grid constraints
Solution Approach 1:
The patent changes the fundamental parameter of the layout system from grid-based to shape-based continuous coordinates. This allows placement and routing to occur at any position rather than being constrained to discrete grid points, enabling optimal compactness and reduced parasitics while maintaining ease of manufacture through automated shape-based algorithms
2Ease of operation
If grid-based routing is used, then routing paths are constrained to grid lines, but this increases wire length and parasitics
Solution Approach 1:
The patent transitions from grid-based routing parameters to continuous shape-based routing parameters. This allows routing paths to follow optimal geometric shapes (such as rectilinear or Manhattan routing) that minimize wire length and parasitics while maintaining ease of operation through automated shape-based routing algorithms that handle off-grid connections naturally
3Measurement precision
If separate placement and routing processes are used, then each process can be optimized independently, but the overall design time increases and iterations are required
Solution Approach 1:
The patent merges separate placement and routing processes into a unified simultaneous place-and-route process. Both placement and routing are performed together using shape-based algorithms, eliminating the need for iterative adjustments and reducing overall design time while maintaining optimization through a single integrated process that considers both placement and routing together
4Ease of operation
If analog circuit placement is performed manually or with traditional tools, then design control is maintained, but the process is time-consuming and does not optimize for performance characteristics
Solution Approach 1:
The patent implements automated shape-based placement and routing that performs design optimization independently. The system automatically places components and routes connections while optimizing for performance characteristics such as parasitics, signal integrity, and compactness, freeing designers from manual labor while maintaining control through configurable design rules and constraints
Data Source
AI summary
Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on random normalized polish expression, and includes cost considerations based on routing of interconnect.