Custom-Tiled Placement Fabric With Transition Rows for Mixed-Height Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor device design methods are limited by the inability to modulate space allocated to cells of differing device sizes in both x and y dimensions, leading to high power consumption and routing challenges due to the restriction of cell rows extending the width of the block, which does not accommodate varying cell heights effectively.
Innovation Solution
A customizable chip fabric is introduced, allowing for the division into regions with varying row patterns and transition regions to accommodate cells of different heights, enabling efficient allocation of space in both dimensions and facilitating proper power and ground rail connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If cell rows of uniform height extend the width of the block, then common power and ground rails can be shared by cells in a block, but the ability to modulate space allocated to cells of differing device sizes is limited
Solution Approach 1:
The chip fabric is divided into multiple regions, each with its own row pattern configuration. This segmentation allows different regions to have different row heights and patterns, enabling space modulation for cells of varying heights while maintaining uniform rows within each region for power and ground rail sharing.
Solution Approach 2:
Different regions of the chip fabric are assigned different row patterns tailored to their specific requirements. High performance blocks receive patterns with taller rows and larger devices, while easy to route blocks receive patterns with shorter rows and smaller devices, optimizing each region's characteristics locally.
2Ease of operation
If cell rows span the entire width of the block, then routing within rows is simplified, but the proportion of cells of different heights cannot be modulated in both x and y dimensions
Solution Approach 1:
The block is segmented into multiple regions that can be tiled together. Each region maintains rows spanning its width for simplified routing, but the collection of regions enables two-dimensional modulation of cell proportions through strategic placement and sizing of regions with different row patterns.
Solution Approach 2:
The solution moves from one-dimensional row patterns to two-dimensional region tiling. By arranging regions with different row patterns in the x-y plane, the system achieves two-dimensional space modulation while preserving the routing simplicity of horizontal rows within each region.
3Ease of manufacture
If uniform height rows are used throughout the block, then manufacturing and power distribution are simplified, but high performance blocks cannot be optimized with taller cells
Solution Approach 1:
Different regions are assigned different row height patterns based on their performance requirements. High performance blocks receive taller rows to accommodate larger devices, while other blocks use shorter rows, with each region maintaining uniform rows for simplified manufacturing and power distribution within that region.
Solution Approach 2:
The chip fabric is segmented into regions with different row height characteristics. This allows uniform row structures within each region for ease of manufacture, while the overall system achieves performance optimization through strategic placement of taller rows in high performance blocks.
4Loss of energy
If cells of different sizes are spaced apart to prevent timing and power interference, then power consumption is reduced, but the block requires more space
Solution Approach 1:
Regions are configured with appropriate row heights and cell densities to contain interference locally. By concentrating cells of similar sizes within regions of matching row patterns, the need for spacing is reduced while preventing interference from propagating across the entire block, thus reducing total area while maintaining low power consumption.
Data Source
Figure 1A~1C
Figure 1D~1E
Figure 2
AI summary
A method includes instantiating a first plurality of rows in a first region of a fabric. The first region has a height corresponding to a sum of heights of the first plurality of rows. The method also includes instantiating a second plurality of rows in a second region of the fabric. The second region is horizontally adjacent to the first region in the fabric. The second region has a height corresponding to a sum of heights of the second plurality of rows. The method further includes determining whether a row of the first plurality of rows is misaligned with a row of the second plurality of rows and adding a transition region between the row of the first plurality of rows and the row of the second plurality of rows in response.