Custom-Tiled Placement Fabrics With Transition Regions for Mixed-Height Cells
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Solution Overview
Problem
Current semiconductor chip design techniques are limited in their ability to modulate space allocation for cells of differing device sizes in two-dimensional layouts, as existing methods only allow for adjustments in the y-dimension, failing to accommodate the diverse power and routing needs of different regions within a chip.
Innovation Solution
The introduction of an adaptive chip fabric design that divides the chip into multiple regions with customizable row patterns, using 'floorboards' with varying heights and widths, allowing for the creation of disjoint rectilinear regions with transition regions to align or separate rows of different heights, enabling efficient power distribution and routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If cells are placed in uniform height rows to enable common power and ground rails, then power distribution is simplified, but the ability to modulate space for cells of different device sizes is limited
Solution Approach 1:
The chip fabric is segmented into multiple regions, each with its own row height pattern. This allows different regions to be optimized for different cell types while maintaining overall power distribution through the segmentation of the fabric structure itself.
Solution Approach 2:
The invention transitions from one-dimensional uniform row patterns to two-dimensional region-based patterns where row heights can vary both vertically and horizontally. This enables space modulation in both dimensions while maintaining power rail alignment through the region-based approach.
2Loss of energy
If cells with different device sizes are spaced apart to prevent timing and power characteristic alterations, then power consumption is reduced, but routing congestion increases
Solution Approach 1:
Different regions of the chip fabric have different row height patterns tailored to local requirements. High-performance regions can use patterns optimized for speed while low-power regions use patterns optimized for energy efficiency, allowing local optimization without global routing congestion.
3Adaptability or versatility
If the chip is divided into multiple regions with varying row patterns, then space allocation for different cell heights is optimized, but row alignment between regions becomes complex
Solution Approach 1:
Transition regions act as intermediaries between regions with different row height patterns. These transition regions facilitate the alignment and connection between adjacent regions, managing the complexity of row alignment while enabling diverse space allocation patterns.
4Speed
If maximum device sizes are used in all cells to ensure performance, then chip performance is improved, but power consumption skyrockets
Solution Approach 1:
Different regions of the chip fabric have different row height patterns tailored to local requirements. High-performance regions can use patterns optimized for speed while low-power regions use patterns optimized for energy efficiency, allowing local optimization without global routing congestion.
Data Source
AI summary
A method includes instantiating a first plurality of rows in a first region of a fabric. The first region has a height corresponding to a sum of heights of the first plurality of rows. The method also includes instantiating a second plurality of rows in a second region of the fabric. The second region is horizontally adjacent to the first region in the fabric. The second region has a height corresponding to a sum of heights of the second plurality of rows. The method further includes determining whether a row of the first plurality of rows is misaligned with a row of the second plurality of rows and adding a transition region between the row of the first plurality of rows and the row of the second plurality of rows in response.