Planar Capacitor Via Layout for Lower Impedance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing planar capacitor structures face high impedance due to restricted current flow from conductive plates to overlying or underlying metal layers, leading to a tradeoff between capacitance density and impedance.
Innovation Solution
The introduction of additional vias that do not pass through the thickness of the electrically conductive plates between metal layers, allowing for reduced impedance without impacting capacitance density. These additional vias are located along existing metal layer traces, simplifying integration and avoiding the need for additional openings in the plates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the diameter or number of vias is increased to decrease impedance, then the impedance is reduced, but the area available to generate capacitance is reduced
Solution Approach 1:
The patent segments the via structure into two types: standard vias that pass through both metal layers and contact multiple plates, and additional vias that contact only the first metal layer and first plate. This segmentation allows the additional vias to contribute to impedance reduction without requiring openings through the capacitor plates, thereby preserving capacitance area.
Solution Approach 2:
The patent introduces vias at a different dimensional level - additional vias are positioned to contact only the first metal layer rather than passing through to the second metal layer. This dimensional variation in via penetration depth allows for increased via density and improved impedance without compromising the capacitor plate structure.
2Object-affected harmful factors
If additional vias are introduced to reduce impedance, then impedance is reduced, but the complexity of the capacitor structure increases
Solution Approach 1:
The additional vias serve multiple functions: they provide additional current paths to reduce impedance, and they can be integrated with existing metal layer traces. The first plate serves both as a capacitor element and as a contact point for the additional vias, reducing the need for separate structures.
Solution Approach 2:
The first plate and first metal layer are designed to self-provide contact points for the additional vias. The additional vias contact the first plate and first metal layer at locations that are already part of the capacitor structure, eliminating the need for separate contact structures and reducing overall complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces capacitor impedance while maintaining capacitance density, thereby improving the electrical performance of integrated circuit designs without compromising the available space for capacitive plates.
Implementation Method 1
MiM capacitors include a first metal layer and a second metal layer over the first metal layer. One or more electrically conductive plates may be provided between the first metal layer and the second metal layer. A high-k dielectric material may surround the stack of conductive plates.
Implementation Method 2
Vias between the first metal layer and the second metal layer are used to contact the plates. The introduction of additional vias that do not pass through the thickness of the electrically conductive plates between metal layers, allowing for reduced impedance
Data Source
AI summary
Embodiments disclosed herein include a capacitor apparatus. In an embodiment, the apparatus comprises a first metal layer and a first plate above the first metal layer, where the first plate is electrically conductive. In an embodiment, a second plate is above the first plate, where the second plate is electrically conductive, and a third plate is above the second plate, where the third plate is electrically conductive. In an embodiment, a second metal layer is above the third plate, and a first via is between the first metal layer and the second metal layer, where the first via contacts the first plate and the third plate. In an embodiment, a second via is between the first metal layer and the second metal layer, where the second via contacts the second plate, and a third via is between the first metal layer and the first plate.