Planar CMOS FET Air Spacer Layout for Source-Substrate Capacitance
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing parasitic capacitance, which increases power consumption and affects device performance, particularly in planar complementary metal oxide semiconductor field effect transistors (CMOS FETs) due to diffused source/drains inducing capacitance between the source/drain region and the substrate.
Innovation Solution
The implementation of air spacers and embedded insulating layers below the source/drain diffusion regions and gate electrodes, formed through specific etching and ion implantation processes, to suppress or eliminate parasitic capacitance, thereby reducing power consumption and enhancing device speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If diffused source/drain structures are used in planar CMOS FETs, then manufacturing is simplified, but parasitic capacitance between source/drain region and substrate increases
Solution Approach 1:
The patent introduces air spacers positioned laterally adjacent to the source/drain regions in a horizontal plane, creating a new spatial dimension for capacitance reduction. This lateral arrangement allows the air spacers to function as parasitic capacitance suppression structures without requiring vertical stacking or complex 3D configurations, thereby maintaining manufacturing simplicity while effectively reducing parasitic capacitance between the source/drain regions and the substrate.
2Loss of energy
If air spacers are introduced to reduce parasitic capacitance, then power consumption decreases, but device structure becomes more complex
Solution Approach 1:
The patent employs air spacers only in specific regions where parasitic capacitance is most problematic, rather than uniformly throughout the entire device. The air spacers are positioned laterally adjacent to the source/drain regions where they provide maximum capacitance reduction benefit, while avoiding unnecessary structural additions in other areas. This selective placement reduces overall device complexity compared to comprehensive approaches.
Solution Approach 2:
The air spacer structure uses a simplified geometric form that can be replicated across multiple source/drain regions using standard lithography and etching processes. The lateral positioning and uniform dimensions allow for easy copying of the same spacer design throughout the device, reducing the complexity of designing and manufacturing different structural variations.
3Object-affected harmful factors
If ion implantation is used to form air spacers, then parasitic capacitance is suppressed, but manufacturing process steps increase
Solution Approach 1:
The patent combines the air spacer formation process with existing ion implantation steps used for source/drain region doping. By utilizing the same ion implantation equipment and process conditions to create both the doped regions and the air spacer structures, the manufacturing process integrates multiple functions into a single operation, thereby suppressing parasitic capacitance without significantly increasing the total number of process steps or reducing manufacturing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, leading to improved device performance with reduced power consumption and increased speed, without the need for costly silicon-on-insulator (SOI) wafers, and allows for adjustable performance through ion implantation conditions.
Implementation Method 1
Existing planer complementary metal oxide semiconductor field effect transistors (CMOS FETs) have diffused source/drains (S/D) that induce parasitic capacitance between the S/D region and the substrate
Implementation Method 2
formed through specific etching and ion implantation processes
Data Source
AI summary
A semiconductor device including a FET includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.