Planar CMOSFET Cross-Shaped Isolation Reduces Leakage
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Solution Overview
Problem
Current planar CMOSFET structures in DRAM chips face issues with current leakage, short channel effects, latch-up, and increased planar areas due to dopant diffusion and ion-implantation processes, which affect the effective channel length and junction isolation, leading to malfunctions and inefficiencies.
Innovation Solution
A novel planar CMOSFET structure with a cross-shape localized isolation region and selectively grown semiconductor regions, using a combination of undoped and heavily doped regions with a composite isolation layer, reduces dopant diffusion and eliminates the need for thermal annealing, thereby minimizing leakage and latch-up while optimizing channel conduction and reducing planar area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion-implantation and thermal annealing processes are used to form source and drain regions, then doping efficiency is improved, but dopant diffusion enlarges source and drain region areas, reducing effective channel length and increasing short channel effects
Solution Approach 1:
The patent extracts and eliminates the thermal annealing process from the manufacturing flow. By using ion-implantation alone without subsequent thermal annealing, the patent prevents dopant diffusion that would otherwise enlarge source and drain regions. This extraction of the harmful thermal process resolves the contradiction by maintaining precise dopant placement while preserving effective channel length.
Solution Approach 2:
The patent replaces the thermal annealing process (thermal energy-based system) with a purely ion-implantation approach. By substituting the thermal field with a direct ion bombardment method, the patent achieves doping without the unwanted side effect of thermal diffusion, thereby maintaining both doping efficiency and channel length precision.
2Reliability
If longer gate length is reserved to accommodate dopant diffusion, then short channel effects are reduced, but device area increases and productivity decreases
Solution Approach 1:
By extracting the thermal annealing step that causes dopant diffusion, the patent eliminates the need to reserve extra gate length as a compensation measure. The direct ion-implantation method provides sufficient dopant placement precision without requiring extended gate structures, thus maintaining reliability while improving area utilization and productivity.
3Area of stationary object
If adjacent n-well and p-well regions are positioned close together to reduce planar area, then area efficiency is improved, but parasitic bipolar devices form creating latch-up paths
Solution Approach 1:
The patent introduces a lightly-doped drain (LDD) region as an intermediary structure between the n-well and p-well regions. This LDD region acts as a buffer that interrupts the parasitic bipolar device formation path, preventing latch-up while allowing the n-well and p-well to be positioned close together for area efficiency.
Solution Approach 2:
The patent applies different doping concentrations locally: heavily doped source/drain regions for efficient conduction, and lightly doped LDD regions specifically at the interfaces between n-well/p-well and source/drain. This local quality differentiation prevents latch-up paths while maintaining overall device compactness.
4Reliability
If multiple thermal annealing processes are applied to reduce connecting resistance, then electrical conductivity is improved, but dopant diffusion continuously enlarges source and drain regions
Solution Approach 1:
The patent extracts and eliminates the multiple thermal annealing processes from the manufacturing sequence. By relying on ion-implantation alone, the patent achieves both low connecting resistance and precise dopant confinement, resolving the contradiction between electrical conductivity improvement and area control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively minimizes current leakage, enhances channel conduction performance, increases immunity to latch-up, and reduces the planar area required for layout isolations, leading to improved reliability and efficiency in DRAM chip operations.
Implementation Method 1
the implanted n-type or p-type dopants in the CMOSFETs 10 will unavoidably diffuse into different directions and enlarge the area of the source and drain regions
Implementation Method 2
selectively grown semiconductor regions
Implementation Method 3
formed by an Ion-implantation plus Thermal Annealing technique to implant n-type dopants into a p-type substrate
Data Source
AI summary
The present invention discloses a planar CMOSFET structure used in the peripheral circuit of DRAM chip and in sense amplifiers of array core circuit of DRAM chip, the planar CMOSFET structure comprises a planar P type MOSFET with a first conductive region, a planar N type MOSFET with a second conductive region, and a cross-shape localized isolation region between the planar P type MOSFET and the planar N type MOSFET; wherein the cross-shape localized isolation region includes a horizontally extended isolation region contacts to a bottom side of the first conductive region and a bottom side of the second conductive region.