Planar Commutation Cell Layout for Low-Inductance Power Converters

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Solution Overview

Problem

Existing power electronics converters face limitations in efficiency and power-to-weight ratio, particularly in aerospace applications, due to high parasitic inductance and heat management challenges.

Innovation Solution

The development of a power electronics converter with a commutation cell that includes a power circuit with multiple power semiconductor switching elements and a gate driver circuit, optimized to reduce parasitic inductance and enhance heat removal through a multi-layer planar carrier substrate and thermal interface layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If power module topology is used with conventional electrical connections, then device availability and cost are acceptable, but parasitic inductance is high and efficiency is limited

Engineering Contradiction:

Improveswitching lossesVSAvoidelectrical connection structure

Core Design Contradiction:

Loss of energyVSDevice complexity

Solution Approach 1:

The patent transitions from conventional three-dimensional wire bonding to a two-dimensional planar electrical connection structure. The carrier substrate provides a flat surface where power semiconductor devices are mounted and electrically connected through trace patterns, eliminating the need for vertical wire bonds and reducing parasitic inductance by shortening current paths.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent integrates multiple functions into the carrier substrate: it serves as both the mechanical mounting platform for power semiconductor devices and the electrical connection network through its conductive trace patterns. This merging of mechanical support and electrical interconnection functions reduces overall system complexity and parasitic elements.

Inventive Principle:

Principle #5Merging (Combining)

2Productivity

If switching frequency is increased to improve efficiency, then power-to-weight ratio improves, but voltage overshoot and heat generation increase due to parasitic inductance

Engineering Contradiction:

Improveswitching frequencyVSAvoidvoltage overshoot and heat

Core Design Contradiction:

ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent acknowledges that higher switching frequencies generate more heat and voltage overshoot, but converts this challenge into a benefit by using the carrier substrate's low-inductance design to minimize voltage overshoot, thereby enabling higher switching frequencies without excessive harmful effects. The planar structure's inherent low parasitic inductance allows the system to operate at higher frequencies where the benefits outweigh the drawbacks.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

3Loss of energy

If electrical connections are optimized to reduce parasitic inductance, then switching losses decrease, but manufacturing complexity increases

Engineering Contradiction:

Improveswitching lossesVSAvoidcarrier substrate fabrication

Core Design Contradiction:

Loss of energyVSEase of manufacture

Solution Approach 1:

The patent replaces the mechanical wire bonding process with a printed circuit board-style trace pattern on the carrier substrate. Instead of manually or automatically bonding wires between components, the electrical connections are created through conductive ink or copper traces deposited during PCB manufacturing, significantly reducing parasitic inductance while simplifying the manufacturing process through standardization.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration achieves high efficiency exceeding 97% and improved power-to-weight ratio, enabling increased operating frequencies and reduced switching losses, while maintaining reliable electrical insulation and heat management.

Implementation Method 1

optimized to reduce parasitic inductance and enhance heat removal through a multi-layer planar carrier substrate and thermal interface layer

Methodology Applied

Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS12323071B2Efficient power electronics arrangement

Publication Date: 2025.06.03 ROLLS ROYCE DEUT LTD & CO KG

AI summary

A power electronics converter includes a substrate and a converter commutation cell including a power circuit. The power circuit includes at least one power semiconductor switching element and at least one capacitor. Each power semiconductor switching element is comprised in a power semiconductor prepackage. An electrical connection side of the respective power semiconductor prepackage is spaced apart in a z direction from the substrate so as to define a prepackage gap between the substrate and the electrical connection side. At least a portion of the prepackage gap is filled with an electrically insulating material having voids. A converter parameter σ defined as an insulation fill factor divided by a maximum void size is greater than or equal to 10/mm. The insulation fill factor is defined as a cumulated volume of the voids subtracted from a volume of the electrically insulating material divided by the volume of the electrically insulating material.