Planar Conductive Layer in Memory Structure
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Solution Overview
Problem
In semiconductor memory devices, the structural design leads to step differences between conductive layers and device-concentrated regions, causing word line opening and linewidth necking issues during lithography, which affect production quality and efficiency.
Innovation Solution
A memory structure with a conductive material extending across both memory and non-memory cell regions, featuring a substantially planar upper surface and concave portions, which eliminates step differences and prevents word line opening and linewidth necking through chemical mechanical polishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory structural design is used, then memory cell functionality is achieved, but step difference occurs at the boundary of conductive layer and device-concentrated region
Solution Approach 1:
The patent introduces a third dimension by forming concave portions in the memory cells that extend downward into the substrate. This vertical dimension allows the conductive material to flow into these concave regions, effectively filling the step difference that would otherwise occur at the boundary between the conductive layer and the device-concentrated region, thereby resolving the manufacturing precision issue while maintaining memory functionality
Solution Approach 2:
The concave portions are formed in advance before the conductive material is deposited. This preliminary action prepares the structure to receive and accommodate the conductive material, ensuring that when the conductive layer is formed, it automatically fills the step differences and creates a planar upper surface without requiring additional corrective processing steps
2Ease of manufacture
If step difference is present, then memory cell structure is formed, but word line opening or necking occurs during lithography
Solution Approach 1:
By creating concave portions that extend vertically into the substrate, the patent provides an additional dimensional space for the conductive material to occupy. This ensures that the conductive layer maintains uniform thickness and creates a planar upper surface, preventing word line opening or necking during lithography while still allowing the memory cell structure to be properly formed
Solution Approach 2:
The patent changes the geometric parameters of the memory cell structure by introducing concave portions with specific depths and dimensions. This parameter modification allows the conductive material to be accommodated in a way that maintains consistent thickness and creates a planar surface, thereby preventing lithography defects while preserving the memory cell's structural integrity
3Ease of operation
If conventional conductive layer design is used, then word line is formed, but defocus phenomenon occurs in lithography process
Solution Approach 1:
The concave portions are formed in advance to create a pre-prepared structure that will naturally accommodate the conductive material. This preliminary preparation ensures that when the conductive layer is deposited, it fills the concave regions and creates a planar upper surface, eliminating the need for additional focus adjustment during lithography and preventing defocus phenomena
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures a flat upper surface for the conductive material, preventing defocusing and necking issues, thereby improving the quality and efficiency of semiconductor memory device production.
Implementation Method 1
a conductive layer is formed on the dielectric structure
Implementation Method 2
chemical mechanical polishing
Data Source
AI summary
A memory structure having a memory cell region and a non-memory cell region is provided. The memory structure includes a plurality of memory cells and a conductive material. The plurality of memory cells are disposed in the memory cell region, wherein a plurality of first concave portions are present in the plurality of memory cells. The conductive material extends across the memory cell region and the non-memory cell region, covers the plurality of memory cells, and extends into the plurality of first concave portions.